0076-media-dt-bindings-cadence-csi2rx-Convert-to-DT-schem.patch 8.2 KB

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  1. From 243b040c3517093309a41877e3c1c6e8a7540071 Mon Sep 17 00:00:00 2001
  2. From: Jack Zhu <[email protected]>
  3. Date: Tue, 23 May 2023 16:56:22 +0800
  4. Subject: [PATCH 076/122] media: dt-bindings: cadence-csi2rx: Convert to DT
  5. schema
  6. Convert DT bindings document for Cadence MIPI-CSI2 RX controller to
  7. DT schema format.
  8. For compatible, new compatibles should not be messed with conversion,
  9. but the original binding did not specify any SoC-specific compatible
  10. string, so add the StarFive compatible string.
  11. Reviewed-by: Krzysztof Kozlowski <[email protected]>
  12. Reviewed-by: Laurent Pinchart <[email protected]>
  13. Signed-off-by: Jack Zhu <[email protected]>
  14. ---
  15. .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------
  16. .../bindings/media/cdns,csi2rx.yaml | 177 ++++++++++++++++++
  17. 2 files changed, 177 insertions(+), 100 deletions(-)
  18. delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt
  19. create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
  20. --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt
  21. +++ /dev/null
  22. @@ -1,100 +0,0 @@
  23. -Cadence MIPI-CSI2 RX controller
  24. -===============================
  25. -
  26. -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
  27. -lanes in input, and 4 different pixel streams in output.
  28. -
  29. -Required properties:
  30. - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
  31. - - reg: base address and size of the memory mapped region
  32. - - clocks: phandles to the clocks driving the controller
  33. - - clock-names: must contain:
  34. - * sys_clk: main clock
  35. - * p_clk: register bank clock
  36. - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
  37. - implemented in hardware, between 0 and 3
  38. -
  39. -Optional properties:
  40. - - phys: phandle to the external D-PHY, phy-names must be provided
  41. - - phy-names: must contain "dphy", if the implementation uses an
  42. - external D-PHY
  43. -
  44. -Required subnodes:
  45. - - ports: A ports node with one port child node per device input and output
  46. - port, in accordance with the video interface bindings defined in
  47. - Documentation/devicetree/bindings/media/video-interfaces.txt. The
  48. - port nodes are numbered as follows:
  49. -
  50. - Port Description
  51. - -----------------------------
  52. - 0 CSI-2 input
  53. - 1 Stream 0 output
  54. - 2 Stream 1 output
  55. - 3 Stream 2 output
  56. - 4 Stream 3 output
  57. -
  58. - The stream output port nodes are optional if they are not
  59. - connected to anything at the hardware level or implemented
  60. - in the design.Since there is only one endpoint per port,
  61. - the endpoints are not numbered.
  62. -
  63. -
  64. -Example:
  65. -
  66. -csi2rx: csi-bridge@0d060000 {
  67. - compatible = "cdns,csi2rx";
  68. - reg = <0x0d060000 0x1000>;
  69. - clocks = <&byteclock>, <&byteclock>
  70. - <&coreclock>, <&coreclock>,
  71. - <&coreclock>, <&coreclock>;
  72. - clock-names = "sys_clk", "p_clk",
  73. - "pixel_if0_clk", "pixel_if1_clk",
  74. - "pixel_if2_clk", "pixel_if3_clk";
  75. -
  76. - ports {
  77. - #address-cells = <1>;
  78. - #size-cells = <0>;
  79. -
  80. - port@0 {
  81. - reg = <0>;
  82. -
  83. - csi2rx_in_sensor: endpoint {
  84. - remote-endpoint = <&sensor_out_csi2rx>;
  85. - clock-lanes = <0>;
  86. - data-lanes = <1 2>;
  87. - };
  88. - };
  89. -
  90. - port@1 {
  91. - reg = <1>;
  92. -
  93. - csi2rx_out_grabber0: endpoint {
  94. - remote-endpoint = <&grabber0_in_csi2rx>;
  95. - };
  96. - };
  97. -
  98. - port@2 {
  99. - reg = <2>;
  100. -
  101. - csi2rx_out_grabber1: endpoint {
  102. - remote-endpoint = <&grabber1_in_csi2rx>;
  103. - };
  104. - };
  105. -
  106. - port@3 {
  107. - reg = <3>;
  108. -
  109. - csi2rx_out_grabber2: endpoint {
  110. - remote-endpoint = <&grabber2_in_csi2rx>;
  111. - };
  112. - };
  113. -
  114. - port@4 {
  115. - reg = <4>;
  116. -
  117. - csi2rx_out_grabber3: endpoint {
  118. - remote-endpoint = <&grabber3_in_csi2rx>;
  119. - };
  120. - };
  121. - };
  122. -};
  123. --- /dev/null
  124. +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
  125. @@ -0,0 +1,177 @@
  126. +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  127. +%YAML 1.2
  128. +---
  129. +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
  130. +$schema: http://devicetree.org/meta-schemas/core.yaml#
  131. +
  132. +title: Cadence MIPI-CSI2 RX controller
  133. +
  134. +maintainers:
  135. + - Maxime Ripard <[email protected]>
  136. +
  137. +description:
  138. + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
  139. + lanes in input, and 4 different pixel streams in output.
  140. +
  141. +properties:
  142. + compatible:
  143. + items:
  144. + - enum:
  145. + - starfive,jh7110-csi2rx
  146. + - const: cdns,csi2rx
  147. +
  148. + reg:
  149. + maxItems: 1
  150. +
  151. + clocks:
  152. + items:
  153. + - description: CSI2Rx system clock
  154. + - description: Gated Register bank clock for APB interface
  155. + - description: pixel Clock for Stream interface 0
  156. + - description: pixel Clock for Stream interface 1
  157. + - description: pixel Clock for Stream interface 2
  158. + - description: pixel Clock for Stream interface 3
  159. +
  160. + clock-names:
  161. + items:
  162. + - const: sys_clk
  163. + - const: p_clk
  164. + - const: pixel_if0_clk
  165. + - const: pixel_if1_clk
  166. + - const: pixel_if2_clk
  167. + - const: pixel_if3_clk
  168. +
  169. + phys:
  170. + maxItems: 1
  171. + description: MIPI D-PHY
  172. +
  173. + phy-names:
  174. + items:
  175. + - const: dphy
  176. +
  177. + ports:
  178. + $ref: /schemas/graph.yaml#/properties/ports
  179. +
  180. + properties:
  181. + port@0:
  182. + $ref: /schemas/graph.yaml#/$defs/port-base
  183. + unevaluatedProperties: false
  184. + description:
  185. + Input port node, single endpoint describing the CSI-2 transmitter.
  186. +
  187. + properties:
  188. + endpoint:
  189. + $ref: video-interfaces.yaml#
  190. + unevaluatedProperties: false
  191. +
  192. + properties:
  193. + bus-type:
  194. + const: 4
  195. +
  196. + clock-lanes:
  197. + const: 0
  198. +
  199. + data-lanes:
  200. + minItems: 1
  201. + maxItems: 4
  202. + items:
  203. + maximum: 4
  204. +
  205. + required:
  206. + - data-lanes
  207. +
  208. + port@1:
  209. + $ref: /schemas/graph.yaml#/properties/port
  210. + description:
  211. + Stream 0 Output port node
  212. +
  213. + port@2:
  214. + $ref: /schemas/graph.yaml#/properties/port
  215. + description:
  216. + Stream 1 Output port node
  217. +
  218. + port@3:
  219. + $ref: /schemas/graph.yaml#/properties/port
  220. + description:
  221. + Stream 2 Output port node
  222. +
  223. + port@4:
  224. + $ref: /schemas/graph.yaml#/properties/port
  225. + description:
  226. + Stream 3 Output port node
  227. +
  228. + required:
  229. + - port@0
  230. +
  231. +required:
  232. + - compatible
  233. + - reg
  234. + - clocks
  235. + - clock-names
  236. + - ports
  237. +
  238. +additionalProperties: false
  239. +
  240. +examples:
  241. + - |
  242. + csi@d060000 {
  243. + compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx";
  244. + reg = <0x0d060000 0x1000>;
  245. + clocks = <&byteclock 7>, <&byteclock 6>,
  246. + <&coreclock 8>, <&coreclock 9>,
  247. + <&coreclock 10>, <&coreclock 11>;
  248. + clock-names = "sys_clk", "p_clk",
  249. + "pixel_if0_clk", "pixel_if1_clk",
  250. + "pixel_if2_clk", "pixel_if3_clk";
  251. + phys = <&csi_phy>;
  252. + phy-names = "dphy";
  253. +
  254. + ports {
  255. + #address-cells = <1>;
  256. + #size-cells = <0>;
  257. +
  258. + port@0 {
  259. + reg = <0>;
  260. +
  261. + csi2rx_in_sensor: endpoint {
  262. + remote-endpoint = <&sensor_out_csi2rx>;
  263. + clock-lanes = <0>;
  264. + data-lanes = <1 2>;
  265. + };
  266. + };
  267. +
  268. + port@1 {
  269. + reg = <1>;
  270. +
  271. + csi2rx_out_grabber0: endpoint {
  272. + remote-endpoint = <&grabber0_in_csi2rx>;
  273. + };
  274. + };
  275. +
  276. + port@2 {
  277. + reg = <2>;
  278. +
  279. + csi2rx_out_grabber1: endpoint {
  280. + remote-endpoint = <&grabber1_in_csi2rx>;
  281. + };
  282. + };
  283. +
  284. + port@3 {
  285. + reg = <3>;
  286. +
  287. + csi2rx_out_grabber2: endpoint {
  288. + remote-endpoint = <&grabber2_in_csi2rx>;
  289. + };
  290. + };
  291. +
  292. + port@4 {
  293. + reg = <4>;
  294. +
  295. + csi2rx_out_grabber3: endpoint {
  296. + remote-endpoint = <&grabber3_in_csi2rx>;
  297. + };
  298. + };
  299. + };
  300. + };
  301. +
  302. +...