0039-soc-mediatek-PMIC-wrap-add-a-slave-specific-struct.patch 10 KB

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  1. From ae593b270b87f9ed6c35dec3ac69dd6bda43c0a0 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Wed, 20 Jan 2016 09:55:08 +0100
  4. Subject: [PATCH 39/78] soc: mediatek: PMIC wrap: add a slave specific struct
  5. This patch adds a new struct pwrap_slv_type that we use to store the slave
  6. specific data. The patch adds 2 new helper functions to access the dew
  7. registers. The slave type is looked up via the wrappers child node.
  8. Signed-off-by: John Crispin <[email protected]>
  9. ---
  10. drivers/soc/mediatek/mtk-pmic-wrap.c | 159 ++++++++++++++++++++++++----------
  11. 1 file changed, 112 insertions(+), 47 deletions(-)
  12. diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
  13. index a2bacda..bcc841e 100644
  14. --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
  15. +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
  16. @@ -69,33 +69,54 @@
  17. PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
  18. PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
  19. -/* macro for slave device wrapper registers */
  20. -#define PWRAP_DEW_BASE 0xbc00
  21. -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
  22. -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
  23. -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
  24. -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
  25. -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
  26. -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
  27. -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
  28. -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
  29. -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
  30. -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
  31. -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
  32. -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
  33. -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
  34. -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
  35. -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
  36. -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
  37. -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
  38. -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
  39. -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
  40. -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
  41. -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
  42. -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
  43. -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
  44. -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
  45. -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
  46. +/* defines for slave device wrapper registers */
  47. +enum dew_regs {
  48. + PWRAP_DEW_BASE,
  49. + PWRAP_DEW_DIO_EN,
  50. + PWRAP_DEW_READ_TEST,
  51. + PWRAP_DEW_WRITE_TEST,
  52. + PWRAP_DEW_CRC_EN,
  53. + PWRAP_DEW_CRC_VAL,
  54. + PWRAP_DEW_MON_GRP_SEL,
  55. + PWRAP_DEW_CIPHER_KEY_SEL,
  56. + PWRAP_DEW_CIPHER_IV_SEL,
  57. + PWRAP_DEW_CIPHER_RDY,
  58. + PWRAP_DEW_CIPHER_MODE,
  59. + PWRAP_DEW_CIPHER_SWRST,
  60. +
  61. + /* MT6397 only regs */
  62. + PWRAP_DEW_EVENT_OUT_EN,
  63. + PWRAP_DEW_EVENT_SRC_EN,
  64. + PWRAP_DEW_EVENT_SRC,
  65. + PWRAP_DEW_EVENT_FLAG,
  66. + PWRAP_DEW_MON_FLAG_SEL,
  67. + PWRAP_DEW_EVENT_TEST,
  68. + PWRAP_DEW_CIPHER_LOAD,
  69. + PWRAP_DEW_CIPHER_START,
  70. +};
  71. +
  72. +static const u32 mt6397_regs[] = {
  73. + [PWRAP_DEW_BASE] = 0xbc00,
  74. + [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
  75. + [PWRAP_DEW_DIO_EN] = 0xbc02,
  76. + [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
  77. + [PWRAP_DEW_EVENT_SRC] = 0xbc06,
  78. + [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
  79. + [PWRAP_DEW_READ_TEST] = 0xbc0a,
  80. + [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
  81. + [PWRAP_DEW_CRC_EN] = 0xbc0e,
  82. + [PWRAP_DEW_CRC_VAL] = 0xbc10,
  83. + [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
  84. + [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
  85. + [PWRAP_DEW_EVENT_TEST] = 0xbc16,
  86. + [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
  87. + [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
  88. + [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
  89. + [PWRAP_DEW_CIPHER_START] = 0xbc1e,
  90. + [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
  91. + [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
  92. + [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
  93. +};
  94. enum pwrap_regs {
  95. PWRAP_MUX_SEL,
  96. @@ -349,16 +370,26 @@ static int mt8135_regs[] = {
  97. [PWRAP_DCM_DBC_PRD] = 0x160,
  98. };
  99. +enum pmic_type {
  100. + PMIC_MT6397,
  101. +};
  102. +
  103. enum pwrap_type {
  104. PWRAP_MT8135,
  105. PWRAP_MT8173,
  106. };
  107. +struct pwrap_slv_type {
  108. + const u32 *dew_regs;
  109. + enum pmic_type type;
  110. +};
  111. +
  112. struct pmic_wrapper {
  113. struct device *dev;
  114. void __iomem *base;
  115. struct regmap *regmap;
  116. const struct pmic_wrapper_type *master;
  117. + const struct pwrap_slv_type *slave;
  118. struct clk *clk_spi;
  119. struct clk *clk_wrap;
  120. struct reset_control *rstc;
  121. @@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
  122. for (i = 0; i < 4; i++) {
  123. pwrap_writel(wrp, i, PWRAP_SIDLY);
  124. - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
  125. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
  126. + &rdata);
  127. if (rdata == PWRAP_DEW_READ_TEST_VAL) {
  128. dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
  129. pass |= 1 << i;
  130. @@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
  131. u32 rdata;
  132. int ret;
  133. - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
  134. + ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
  135. + &rdata);
  136. if (ret)
  137. return 0;
  138. @@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  139. }
  140. /* Config cipher mode @PMIC */
  141. - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
  142. - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
  143. - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
  144. - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
  145. - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
  146. - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
  147. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
  148. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
  149. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
  150. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
  151. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
  152. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
  153. /* wait for cipher data ready@AP */
  154. ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
  155. @@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  156. }
  157. /* wait for cipher mode idle */
  158. - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
  159. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
  160. ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  161. if (ret) {
  162. dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
  163. @@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
  164. pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
  165. /* Write Test */
  166. - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
  167. - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
  168. - (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
  169. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
  170. + PWRAP_DEW_WRITE_TEST_VAL) ||
  171. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
  172. + &rdata) ||
  173. + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
  174. dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
  175. return -EFAULT;
  176. }
  177. @@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  178. writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
  179. /* enable PMIC event out and sources */
  180. - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
  181. - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
  182. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
  183. + 0x1) ||
  184. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
  185. + 0xffff)) {
  186. dev_err(wrp->dev, "enable dewrap fail\n");
  187. return -EFAULT;
  188. }
  189. @@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
  190. static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
  191. {
  192. /* PMIC_DEWRAP enables */
  193. - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
  194. - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
  195. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
  196. + 0x1) ||
  197. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
  198. + 0xffff)) {
  199. dev_err(wrp->dev, "enable dewrap fail\n");
  200. return -EFAULT;
  201. }
  202. @@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  203. return ret;
  204. /* Enable dual IO mode */
  205. - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
  206. + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
  207. /* Check IDLE & INIT_DONE in advance */
  208. ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
  209. @@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  210. pwrap_writel(wrp, 1, PWRAP_DIO_EN);
  211. /* Read Test */
  212. - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
  213. + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
  214. if (rdata != PWRAP_DEW_READ_TEST_VAL) {
  215. dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
  216. PWRAP_DEW_READ_TEST_VAL, rdata);
  217. @@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
  218. return ret;
  219. /* Signature checking - using CRC */
  220. - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
  221. + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
  222. return -EFAULT;
  223. pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
  224. pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
  225. - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
  226. + pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
  227. + PWRAP_SIG_ADR);
  228. pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
  229. if (wrp->master->type == PWRAP_MT8135)
  230. @@ -818,6 +858,21 @@ static const struct regmap_config pwrap_regmap_config = {
  231. .max_register = 0xffff,
  232. };
  233. +static const struct pwrap_slv_type pmic_mt6397 = {
  234. + .dew_regs = mt6397_regs,
  235. + .type = PMIC_MT6397,
  236. +};
  237. +
  238. +static const struct of_device_id of_slave_match_tbl[] = {
  239. + {
  240. + .compatible = "mediatek,mt6397",
  241. + .data = &pmic_mt6397,
  242. + }, {
  243. + /* sentinel */
  244. + }
  245. +};
  246. +MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
  247. +
  248. static struct pmic_wrapper_type pwrap_mt8135 = {
  249. .regs = mt8135_regs,
  250. .type = PWRAP_MT8135,
  251. @@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_device *pdev)
  252. struct device_node *np = pdev->dev.of_node;
  253. const struct of_device_id *of_id =
  254. of_match_device(of_pwrap_match_tbl, &pdev->dev);
  255. + const struct of_device_id *of_slave_id = NULL;
  256. struct resource *res;
  257. + if (pdev->dev.of_node->child)
  258. + of_slave_id = of_match_node(of_slave_match_tbl,
  259. + pdev->dev.of_node->child);
  260. + if (!of_slave_id) {
  261. + dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
  262. + return -EINVAL;
  263. + }
  264. +
  265. wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
  266. if (!wrp)
  267. return -ENOMEM;
  268. @@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_device *pdev)
  269. platform_set_drvdata(pdev, wrp);
  270. wrp->master = of_id->data;
  271. + wrp->slave = of_slave_id->data;
  272. wrp->dev = &pdev->dev;
  273. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
  274. --
  275. 1.7.10.4