armada-7040-mochabin.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /*
  3. * Device Tree file for Globalscale MOCHAbin
  4. * Copyright (C) 2019 Globalscale technologies, Inc.
  5. * Copyright (C) 2021 Sartura Ltd.
  6. *
  7. */
  8. /dts-v1/;
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include "armada-7040.dtsi"
  11. / {
  12. model = "Globalscale MOCHAbin";
  13. compatible = "globalscale,mochabin", "marvell,armada7040",
  14. "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. aliases {
  19. ethernet0 = &cp0_eth0;
  20. ethernet1 = &cp0_eth1;
  21. ethernet2 = &cp0_eth2;
  22. ethernet3 = &swport1;
  23. ethernet4 = &swport2;
  24. ethernet5 = &swport3;
  25. ethernet6 = &swport4;
  26. };
  27. /* SFP+ 10G */
  28. sfp_eth0: sfp-eth0 {
  29. compatible = "sff,sfp";
  30. i2c-bus = <&cp0_i2c1>;
  31. los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
  32. mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
  33. tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
  34. tx-fault-gpio = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
  35. };
  36. /* SFP 1G */
  37. sfp_eth2: sfp-eth2 {
  38. compatible = "sff,sfp";
  39. i2c-bus = <&cp0_i2c0>;
  40. los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
  41. mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
  42. tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
  43. tx-fault-gpio = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
  44. };
  45. };
  46. /* microUSB UART console */
  47. &uart0 {
  48. status = "okay";
  49. pinctrl-0 = <&uart0_pins>;
  50. pinctrl-names = "default";
  51. };
  52. /* eMMC */
  53. &ap_sdhci0 {
  54. status = "okay";
  55. bus-width = <4>;
  56. non-removable;
  57. /delete-property/ marvell,xenon-phy-slow-mode;
  58. no-1-8-v;
  59. };
  60. &cp0_pinctrl {
  61. cp0_uart0_pins: cp0-uart0-pins {
  62. marvell,pins = "mpp6", "mpp7";
  63. marvell,function = "uart0";
  64. };
  65. cp0_spi0_pins: cp0-spi0-pins {
  66. marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
  67. marvell,function = "spi0";
  68. };
  69. cp0_spi1_pins: cp0-spi1-pins {
  70. marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
  71. marvell,function = "spi1";
  72. };
  73. cp0_i2c0_pins: cp0-i2c0-pins {
  74. marvell,pins = "mpp37", "mpp38";
  75. marvell,function = "i2c0";
  76. };
  77. cp0_i2c1_pins: cp0-i2c1-pins {
  78. marvell,pins = "mpp2", "mpp3";
  79. marvell,function = "i2c1";
  80. };
  81. pca9554_int_pins: pca9554-int-pins {
  82. marvell,pins = "mpp27";
  83. marvell,function = "gpio";
  84. };
  85. cp0_rgmii1_pins: cp0-rgmii1-pins {
  86. marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
  87. "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
  88. marvell,function = "ge1";
  89. };
  90. is31_sdb_pins: is31-sdb-pins {
  91. marvell,pins = "mpp30";
  92. marvell,function = "gpio";
  93. };
  94. cp0_pcie_reset_pins: cp0-pcie-reset-pins {
  95. marvell,pins = "mpp9";
  96. marvell,function = "gpio";
  97. };
  98. cp0_switch_pins: cp0-switch-pins {
  99. marvell,pins = "mpp0", "mpp1";
  100. marvell,function = "gpio";
  101. };
  102. cp0_phy_pins: cp0-phy-pins {
  103. marvell,pins = "mpp12";
  104. marvell,function = "gpio";
  105. };
  106. };
  107. /* mikroBUS UART */
  108. &cp0_uart0 {
  109. status = "okay";
  110. pinctrl-names = "default";
  111. pinctrl-0 = <&cp0_uart0_pins>;
  112. };
  113. /* mikroBUS SPI */
  114. &cp0_spi0 {
  115. status = "okay";
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&cp0_spi0_pins>;
  118. };
  119. /* SPI-NOR */
  120. &cp0_spi1{
  121. status = "okay";
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&cp0_spi1_pins>;
  124. spi-flash@0 {
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. compatible = "jedec,spi-nor";
  128. reg = <0>;
  129. spi-max-frequency = <20000000>;
  130. partitions {
  131. compatible = "fixed-partitions";
  132. #address-cells = <1>;
  133. #size-cells = <1>;
  134. partition@0 {
  135. label = "u-boot";
  136. reg = <0x0 0x3e0000>;
  137. read-only;
  138. };
  139. partition@3e0000 {
  140. label = "hw-info";
  141. reg = <0x3e0000 0x10000>;
  142. read-only;
  143. };
  144. partition@3f0000 {
  145. label = "u-boot-env";
  146. reg = <0x3f0000 0x10000>;
  147. };
  148. };
  149. };
  150. };
  151. /* mikroBUS, 1G SFP and GPIO expander */
  152. &cp0_i2c0 {
  153. status = "okay";
  154. pinctrl-names = "default";
  155. pinctrl-0 = <&cp0_i2c0_pins>;
  156. clock-frequency = <100000>;
  157. sfp_gpio: pca9554@39 {
  158. compatible = "nxp,pca9554";
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&pca9554_int_pins>;
  161. reg = <0x39>;
  162. interrupt-parent = <&cp0_gpio1>;
  163. interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  164. interrupt-controller;
  165. #interrupt-cells = <2>;
  166. gpio-controller;
  167. #gpio-cells = <2>;
  168. /*
  169. * IO0_0: SFP+_TX_FAULT
  170. * IO0_1: SFP+_TX_DISABLE
  171. * IO0_2: SFP+_PRSNT
  172. * IO0_3: SFP+_LOSS
  173. * IO0_4: SFP_TX_FAULT
  174. * IO0_5: SFP_TX_DISABLE
  175. * IO0_6: SFP_PRSNT
  176. * IO0_7: SFP_LOSS
  177. */
  178. };
  179. };
  180. /* IS31FL3199, mini-PCIe and 10G SFP+ */
  181. &cp0_i2c1 {
  182. status = "okay";
  183. pinctrl-names = "default";
  184. pinctrl-0 = <&cp0_i2c1_pins>;
  185. clock-frequency = <100000>;
  186. leds@64 {
  187. compatible = "issi,is31fl3199";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&is31_sdb_pins>;
  192. shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
  193. reg = <0x64>;
  194. led1_red: led@1 {
  195. label = "red:led1";
  196. reg = <1>;
  197. led-max-microamp = <20000>;
  198. };
  199. led1_green: led@2 {
  200. label = "green:led1";
  201. reg = <2>;
  202. };
  203. led1_blue: led@3 {
  204. label = "blue:led1";
  205. reg = <3>;
  206. };
  207. led2_red: led@4 {
  208. label = "red:led2";
  209. reg = <4>;
  210. };
  211. led2_green: led@5 {
  212. label = "green:led2";
  213. reg = <5>;
  214. };
  215. led2_blue: led@6 {
  216. label = "blue:led2";
  217. reg = <6>;
  218. };
  219. led3_red: led@7 {
  220. label = "red:led3";
  221. reg = <7>;
  222. };
  223. led3_green: led@8 {
  224. label = "green:led3";
  225. reg = <8>;
  226. };
  227. led3_blue: led@9 {
  228. label = "blue:led3";
  229. reg = <9>;
  230. };
  231. };
  232. };
  233. &cp0_mdio {
  234. status = "okay";
  235. /* 88E1512 PHY */
  236. eth2phy: ethernet-phy@1 {
  237. reg = <1>;
  238. sfp = <&sfp_eth2>;
  239. pinctrl-names = "default";
  240. pinctrl-0 = <&cp0_phy_pins>;
  241. reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
  242. };
  243. /* 88E6141 Topaz switch */
  244. switch: switch@3 {
  245. compatible = "marvell,mv88e6085";
  246. #address-cells = <1>;
  247. #size-cells = <0>;
  248. reg = <3>;
  249. pinctrl-names = "default";
  250. pinctrl-0 = <&cp0_switch_pins>;
  251. reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
  252. interrupt-parent = <&cp0_gpio1>;
  253. interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
  254. ports {
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. swport1: port@1 {
  258. reg = <1>;
  259. label = "lan0";
  260. phy-handle = <&swphy1>;
  261. };
  262. swport2: port@2 {
  263. reg = <2>;
  264. label = "lan1";
  265. phy-handle = <&swphy2>;
  266. };
  267. swport3: port@3 {
  268. reg = <3>;
  269. label = "lan2";
  270. phy-handle = <&swphy3>;
  271. };
  272. swport4: port@4 {
  273. reg = <4>;
  274. label = "lan3";
  275. phy-handle = <&swphy4>;
  276. };
  277. port@5 {
  278. reg = <5>;
  279. ethernet = <&cp0_eth1>;
  280. phy-mode = "2500base-x";
  281. managed = "in-band-status";
  282. };
  283. };
  284. mdio {
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. swphy1: swphy1@17 {
  288. reg = <17>;
  289. };
  290. swphy2: swphy2@18 {
  291. reg = <18>;
  292. };
  293. swphy3: swphy3@19 {
  294. reg = <19>;
  295. };
  296. swphy4: swphy4@20 {
  297. reg = <20>;
  298. };
  299. };
  300. };
  301. };
  302. &cp0_ethernet {
  303. status = "okay";
  304. };
  305. /* 10G SFP+ */
  306. &cp0_eth0 {
  307. status = "okay";
  308. phy-mode = "10gbase-r";
  309. phys = <&cp0_comphy4 0>;
  310. managed = "in-band-status";
  311. sfp = <&sfp_eth0>;
  312. };
  313. /* Topaz switch uplink */
  314. &cp0_eth1 {
  315. status = "okay";
  316. phy-mode = "2500base-x";
  317. phys = <&cp0_comphy0 1>;
  318. fixed-link {
  319. speed = <2500>;
  320. full-duplex;
  321. };
  322. };
  323. /* 1G SFP or 1G RJ45 */
  324. &cp0_eth2 {
  325. status = "okay";
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&cp0_rgmii1_pins>;
  328. phy = <&eth2phy>;
  329. phy-mode = "rgmii-id";
  330. };
  331. /* SMSC USB5434B hub */
  332. &cp0_usb3_0 {
  333. status = "okay";
  334. phys = <&cp0_comphy1 0>;
  335. phy-names = "cp0-usb3h0-comphy";
  336. };
  337. /* miniPCI-E USB */
  338. &cp0_usb3_1 {
  339. status = "okay";
  340. };
  341. &cp0_sata0 {
  342. status = "okay";
  343. /* 7 + 12 SATA connector (J24) */
  344. sata-port@0 {
  345. phys = <&cp0_comphy2 0>;
  346. phy-names = "cp0-sata0-0-phy";
  347. };
  348. /* M.2-2250 B-key (J39) */
  349. sata-port@1 {
  350. phys = <&cp0_comphy3 1>;
  351. phy-names = "cp0-sata0-1-phy";
  352. };
  353. };
  354. /* miniPCI-E (J5) */
  355. &cp0_pcie2 {
  356. status = "okay";
  357. pinctrl-names = "default";
  358. pinctrl-0 = <&cp0_pcie_reset_pins>;
  359. phys = <&cp0_comphy5 2>;
  360. phy-names = "cp0-pcie2-x1-phy";
  361. reset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
  362. ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;
  363. };