007-v6.3-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch 9.0 KB

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  1. From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
  2. From: Chukun Pan <[email protected]>
  3. Date: Sat, 3 Dec 2022 15:41:49 +0800
  4. Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
  5. Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
  6. This device is similar to the NanoPi R2S, and has a 16MB
  7. SPI NOR (mx25l12805d). The reset button is changed to
  8. directly reset the power supply, another detail is that
  9. both network ports have independent MAC addresses.
  10. Signed-off-by: Chukun Pan <[email protected]>
  11. Link: https://lore.kernel.org/r/[email protected]
  12. Signed-off-by: Heiko Stuebner <[email protected]>
  13. ---
  14. arch/arm64/boot/dts/rockchip/Makefile | 1 +
  15. .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
  16. 2 files changed, 374 insertions(+)
  17. create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
  18. --- a/arch/arm64/boot/dts/rockchip/Makefile
  19. +++ b/arch/arm64/boot/dts/rockchip/Makefile
  20. @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
  21. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
  22. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
  23. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
  24. +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
  25. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  26. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
  27. dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
  28. --- /dev/null
  29. +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
  30. @@ -0,0 +1,373 @@
  31. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  32. +/*
  33. + * Based on rk3328-nanopi-r2s.dts, which is:
  34. + * Copyright (c) 2020 David Bauer <[email protected]>
  35. + */
  36. +
  37. +/dts-v1/;
  38. +
  39. +#include <dt-bindings/gpio/gpio.h>
  40. +#include <dt-bindings/leds/common.h>
  41. +#include "rk3328.dtsi"
  42. +
  43. +/ {
  44. + model = "Xunlong Orange Pi R1 Plus";
  45. + compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
  46. +
  47. + aliases {
  48. + ethernet1 = &rtl8153;
  49. + mmc0 = &sdmmc;
  50. + };
  51. +
  52. + chosen {
  53. + stdout-path = "serial2:1500000n8";
  54. + };
  55. +
  56. + gmac_clk: gmac-clock {
  57. + compatible = "fixed-clock";
  58. + clock-frequency = <125000000>;
  59. + clock-output-names = "gmac_clkin";
  60. + #clock-cells = <0>;
  61. + };
  62. +
  63. + leds {
  64. + compatible = "gpio-leds";
  65. + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
  66. + pinctrl-names = "default";
  67. +
  68. + led-0 {
  69. + function = LED_FUNCTION_LAN;
  70. + color = <LED_COLOR_ID_GREEN>;
  71. + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
  72. + };
  73. +
  74. + led-1 {
  75. + function = LED_FUNCTION_STATUS;
  76. + color = <LED_COLOR_ID_RED>;
  77. + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
  78. + linux,default-trigger = "heartbeat";
  79. + };
  80. +
  81. + led-2 {
  82. + function = LED_FUNCTION_WAN;
  83. + color = <LED_COLOR_ID_GREEN>;
  84. + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
  85. + };
  86. + };
  87. +
  88. + vcc_sd: sdmmc-regulator {
  89. + compatible = "regulator-fixed";
  90. + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
  91. + pinctrl-0 = <&sdmmc0m1_pin>;
  92. + pinctrl-names = "default";
  93. + regulator-name = "vcc_sd";
  94. + regulator-boot-on;
  95. + vin-supply = <&vcc_io>;
  96. + };
  97. +
  98. + vcc_sys: vcc-sys-regulator {
  99. + compatible = "regulator-fixed";
  100. + regulator-name = "vcc_sys";
  101. + regulator-always-on;
  102. + regulator-boot-on;
  103. + regulator-min-microvolt = <5000000>;
  104. + regulator-max-microvolt = <5000000>;
  105. + };
  106. +
  107. + vdd_5v_lan: vdd-5v-lan-regulator {
  108. + compatible = "regulator-fixed";
  109. + enable-active-high;
  110. + gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
  111. + pinctrl-0 = <&lan_vdd_pin>;
  112. + pinctrl-names = "default";
  113. + regulator-name = "vdd_5v_lan";
  114. + regulator-always-on;
  115. + regulator-boot-on;
  116. + vin-supply = <&vcc_sys>;
  117. + };
  118. +};
  119. +
  120. +&cpu0 {
  121. + cpu-supply = <&vdd_arm>;
  122. +};
  123. +
  124. +&cpu1 {
  125. + cpu-supply = <&vdd_arm>;
  126. +};
  127. +
  128. +&cpu2 {
  129. + cpu-supply = <&vdd_arm>;
  130. +};
  131. +
  132. +&cpu3 {
  133. + cpu-supply = <&vdd_arm>;
  134. +};
  135. +
  136. +&display_subsystem {
  137. + status = "disabled";
  138. +};
  139. +
  140. +&gmac2io {
  141. + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
  142. + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
  143. + clock_in_out = "input";
  144. + phy-handle = <&rtl8211e>;
  145. + phy-mode = "rgmii";
  146. + phy-supply = <&vcc_io>;
  147. + pinctrl-0 = <&rgmiim1_pins>;
  148. + pinctrl-names = "default";
  149. + snps,aal;
  150. + rx_delay = <0x18>;
  151. + tx_delay = <0x24>;
  152. + status = "okay";
  153. +
  154. + mdio {
  155. + compatible = "snps,dwmac-mdio";
  156. + #address-cells = <1>;
  157. + #size-cells = <0>;
  158. +
  159. + rtl8211e: ethernet-phy@1 {
  160. + reg = <1>;
  161. + pinctrl-0 = <&eth_phy_reset_pin>;
  162. + pinctrl-names = "default";
  163. + reset-assert-us = <10000>;
  164. + reset-deassert-us = <50000>;
  165. + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  166. + };
  167. + };
  168. +};
  169. +
  170. +&i2c1 {
  171. + status = "okay";
  172. +
  173. + rk805: pmic@18 {
  174. + compatible = "rockchip,rk805";
  175. + reg = <0x18>;
  176. + interrupt-parent = <&gpio1>;
  177. + interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
  178. + #clock-cells = <1>;
  179. + clock-output-names = "xin32k", "rk805-clkout2";
  180. + gpio-controller;
  181. + #gpio-cells = <2>;
  182. + pinctrl-0 = <&pmic_int_l>;
  183. + pinctrl-names = "default";
  184. + rockchip,system-power-controller;
  185. + wakeup-source;
  186. +
  187. + vcc1-supply = <&vcc_sys>;
  188. + vcc2-supply = <&vcc_sys>;
  189. + vcc3-supply = <&vcc_sys>;
  190. + vcc4-supply = <&vcc_sys>;
  191. + vcc5-supply = <&vcc_io>;
  192. + vcc6-supply = <&vcc_sys>;
  193. +
  194. + regulators {
  195. + vdd_log: DCDC_REG1 {
  196. + regulator-name = "vdd_log";
  197. + regulator-always-on;
  198. + regulator-boot-on;
  199. + regulator-min-microvolt = <712500>;
  200. + regulator-max-microvolt = <1450000>;
  201. + regulator-ramp-delay = <12500>;
  202. +
  203. + regulator-state-mem {
  204. + regulator-on-in-suspend;
  205. + regulator-suspend-microvolt = <1000000>;
  206. + };
  207. + };
  208. +
  209. + vdd_arm: DCDC_REG2 {
  210. + regulator-name = "vdd_arm";
  211. + regulator-always-on;
  212. + regulator-boot-on;
  213. + regulator-min-microvolt = <712500>;
  214. + regulator-max-microvolt = <1450000>;
  215. + regulator-ramp-delay = <12500>;
  216. +
  217. + regulator-state-mem {
  218. + regulator-on-in-suspend;
  219. + regulator-suspend-microvolt = <950000>;
  220. + };
  221. + };
  222. +
  223. + vcc_ddr: DCDC_REG3 {
  224. + regulator-name = "vcc_ddr";
  225. + regulator-always-on;
  226. + regulator-boot-on;
  227. +
  228. + regulator-state-mem {
  229. + regulator-on-in-suspend;
  230. + };
  231. + };
  232. +
  233. + vcc_io: DCDC_REG4 {
  234. + regulator-name = "vcc_io";
  235. + regulator-always-on;
  236. + regulator-boot-on;
  237. + regulator-min-microvolt = <3300000>;
  238. + regulator-max-microvolt = <3300000>;
  239. +
  240. + regulator-state-mem {
  241. + regulator-on-in-suspend;
  242. + regulator-suspend-microvolt = <3300000>;
  243. + };
  244. + };
  245. +
  246. + vcc_18: LDO_REG1 {
  247. + regulator-name = "vcc_18";
  248. + regulator-always-on;
  249. + regulator-boot-on;
  250. + regulator-min-microvolt = <1800000>;
  251. + regulator-max-microvolt = <1800000>;
  252. +
  253. + regulator-state-mem {
  254. + regulator-on-in-suspend;
  255. + regulator-suspend-microvolt = <1800000>;
  256. + };
  257. + };
  258. +
  259. + vcc18_emmc: LDO_REG2 {
  260. + regulator-name = "vcc18_emmc";
  261. + regulator-always-on;
  262. + regulator-boot-on;
  263. + regulator-min-microvolt = <1800000>;
  264. + regulator-max-microvolt = <1800000>;
  265. +
  266. + regulator-state-mem {
  267. + regulator-on-in-suspend;
  268. + regulator-suspend-microvolt = <1800000>;
  269. + };
  270. + };
  271. +
  272. + vdd_10: LDO_REG3 {
  273. + regulator-name = "vdd_10";
  274. + regulator-always-on;
  275. + regulator-boot-on;
  276. + regulator-min-microvolt = <1000000>;
  277. + regulator-max-microvolt = <1000000>;
  278. +
  279. + regulator-state-mem {
  280. + regulator-on-in-suspend;
  281. + regulator-suspend-microvolt = <1000000>;
  282. + };
  283. + };
  284. + };
  285. + };
  286. +};
  287. +
  288. +&io_domains {
  289. + pmuio-supply = <&vcc_io>;
  290. + vccio1-supply = <&vcc_io>;
  291. + vccio2-supply = <&vcc18_emmc>;
  292. + vccio3-supply = <&vcc_io>;
  293. + vccio4-supply = <&vcc_io>;
  294. + vccio5-supply = <&vcc_io>;
  295. + vccio6-supply = <&vcc_io>;
  296. + status = "okay";
  297. +};
  298. +
  299. +&pinctrl {
  300. + gmac2io {
  301. + eth_phy_reset_pin: eth-phy-reset-pin {
  302. + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
  303. + };
  304. + };
  305. +
  306. + leds {
  307. + lan_led_pin: lan-led-pin {
  308. + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
  309. + };
  310. +
  311. + sys_led_pin: sys-led-pin {
  312. + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
  313. + };
  314. +
  315. + wan_led_pin: wan-led-pin {
  316. + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
  317. + };
  318. + };
  319. +
  320. + lan {
  321. + lan_vdd_pin: lan-vdd-pin {
  322. + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  323. + };
  324. + };
  325. +
  326. + pmic {
  327. + pmic_int_l: pmic-int-l {
  328. + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
  329. + };
  330. + };
  331. +};
  332. +
  333. +&pwm2 {
  334. + status = "okay";
  335. +};
  336. +
  337. +&sdmmc {
  338. + bus-width = <4>;
  339. + cap-sd-highspeed;
  340. + disable-wp;
  341. + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
  342. + pinctrl-names = "default";
  343. + vmmc-supply = <&vcc_sd>;
  344. + status = "okay";
  345. +};
  346. +
  347. +&spi0 {
  348. + status = "okay";
  349. +
  350. + flash@0 {
  351. + compatible = "jedec,spi-nor";
  352. + reg = <0>;
  353. + spi-max-frequency = <50000000>;
  354. + };
  355. +};
  356. +
  357. +&tsadc {
  358. + rockchip,hw-tshut-mode = <0>;
  359. + rockchip,hw-tshut-polarity = <0>;
  360. + status = "okay";
  361. +};
  362. +
  363. +&u2phy {
  364. + status = "okay";
  365. +};
  366. +
  367. +&u2phy_host {
  368. + status = "okay";
  369. +};
  370. +
  371. +&u2phy_otg {
  372. + status = "okay";
  373. +};
  374. +
  375. +&uart2 {
  376. + status = "okay";
  377. +};
  378. +
  379. +&usb20_otg {
  380. + dr_mode = "host";
  381. + status = "okay";
  382. +};
  383. +
  384. +&usbdrd3 {
  385. + dr_mode = "host";
  386. + status = "okay";
  387. + #address-cells = <1>;
  388. + #size-cells = <0>;
  389. +
  390. + /* Second port is for USB 3.0 */
  391. + rtl8153: device@2 {
  392. + compatible = "usbbda,8153";
  393. + reg = <2>;
  394. + };
  395. +};
  396. +
  397. +&usb_host0_ehci {
  398. + status = "okay";
  399. +};
  400. +
  401. +&usb_host0_ohci {
  402. + status = "okay";
  403. +};