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- From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
- Date: Fri, 27 Jul 2018 12:39:01 +0200
- Subject: [PATCH] Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe
- erratum"
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- This reverts commit 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175.
- Enabling ExternalSync caused a regression for BCM4718A1 (used e.g. in
- Netgear E3000 and ASUS RT-N16): it simply hangs during PCIe
- initialization. It's likely that BCM4717A1 is also affected.
- I didn't notice that earlier as the only BCM47XX devices with PCIe I
- own are:
- 1) BCM4706 with 2 x 14e4:4331
- 2) BCM4706 with 14e4:4360 and 14e4:4331
- it appears that BCM4706 is unaffected.
- While BCM5300X-ES300-RDS.pdf seems to document that erratum and its
- workarounds (according to quotes provided by Tokunori) it seems not even
- Broadcom follows them.
- According to the provided info Broadcom should define CONF7_ES in their
- SDK's mipsinc.h and implement workaround in the si_mips_init(). Checking
- both didn't reveal such code. It *could* mean Broadcom also had some
- problems with the given workaround.
- Reported-by: Michael Marley <[email protected]>
- Cc: Tokunori Ikegami <[email protected]>
- Cc: Paul Burton <[email protected]>
- Cc: Hauke Mehrtens <[email protected]>
- Cc: Chris Packham <[email protected]>
- Cc: [email protected]
- Cc: James Hogan <[email protected]>
- Signed-off-by: Rafał Miłecki <[email protected]>
- ---
- arch/mips/bcm47xx/setup.c | 6 ------
- arch/mips/include/asm/mipsregs.h | 3 ---
- 2 files changed, 9 deletions(-)
- --- a/arch/mips/bcm47xx/setup.c
- +++ b/arch/mips/bcm47xx/setup.c
- @@ -212,12 +212,6 @@ static int __init bcm47xx_cpu_fixes(void
- */
- if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
- cpu_wait = NULL;
- -
- - /*
- - * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
- - * Enable ExternalSync for sync instruction to take effect
- - */
- - set_c0_config7(MIPS_CONF7_ES);
- break;
- #endif
- }
- --- a/arch/mips/include/asm/mipsregs.h
- +++ b/arch/mips/include/asm/mipsregs.h
- @@ -680,8 +680,6 @@
- #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
-
- #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
- -/* ExternalSync */
- -#define MIPS_CONF7_ES (_ULCAST_(1) << 8)
-
- #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
- #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
- @@ -2747,7 +2745,6 @@ __BUILD_SET_C0(status)
- __BUILD_SET_C0(cause)
- __BUILD_SET_C0(config)
- __BUILD_SET_C0(config5)
- -__BUILD_SET_C0(config7)
- __BUILD_SET_C0(intcontrol)
- __BUILD_SET_C0(intctl)
- __BUILD_SET_C0(srsmap)
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