100-21-mtd-spi-nor-add-more-flash-ids.patch 3.0 KB

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  1. From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
  2. From: Weijie Gao <[email protected]>
  3. Date: Wed, 27 Jul 2022 16:32:17 +0800
  4. Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
  5. Add more spi-nor flash ids
  6. Signed-off-by: Weijie Gao <[email protected]>
  7. ---
  8. drivers/mtd/spi/spi-nor-core.c | 1 +
  9. drivers/mtd/spi/spi-nor-ids.c | 23 ++++++++++++++++++++++-
  10. 2 files changed, 23 insertions(+), 1 deletion(-)
  11. --- a/drivers/mtd/spi/spi-nor-core.c
  12. +++ b/drivers/mtd/spi/spi-nor-core.c
  13. @@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor
  14. case SNOR_MFR_ISSI:
  15. case SNOR_MFR_MACRONIX:
  16. case SNOR_MFR_WINBOND:
  17. + case SNOR_MFR_EON:
  18. if (need_wren)
  19. write_enable(nor);
  20. --- a/drivers/mtd/spi/spi-nor-ids.c
  21. +++ b/drivers/mtd/spi/spi-nor-ids.c
  22. @@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] =
  23. { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
  24. { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
  25. { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
  26. - { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
  27. + { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  28. + { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  29. { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
  30. #endif
  31. #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
  32. @@ -149,6 +150,11 @@ const struct flash_info spi_nor_ids[] =
  33. {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
  34. SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
  35. {
  36. + INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
  37. + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  38. + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  39. + },
  40. + {
  41. INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
  42. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  43. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  44. @@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] =
  45. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  46. },
  47. {
  48. + INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512,
  49. + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  50. + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  51. + },
  52. + {
  53. + INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024,
  54. + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  55. + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  56. + },
  57. + {
  58. INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
  59. SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  60. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  61. @@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] =
  62. SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  63. },
  64. { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  65. + {
  66. + INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024,
  67. + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
  68. + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
  69. + },
  70. { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  71. { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  72. { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },