410-add-linksys-e8450.patch 13 KB

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  1. --- /dev/null
  2. +++ b/configs/mt7622_linksys_e8450_defconfig
  3. @@ -0,0 +1,140 @@
  4. +CONFIG_ARM=y
  5. +CONFIG_POSITION_INDEPENDENT=y
  6. +CONFIG_ARCH_MEDIATEK=y
  7. +CONFIG_TARGET_MT7622=y
  8. +CONFIG_TEXT_BASE=0x41e00000
  9. +CONFIG_SYS_MALLOC_F_LEN=0x4000
  10. +CONFIG_SYS_LOAD_ADDR=0x40080000
  11. +CONFIG_USE_DEFAULT_ENV_FILE=y
  12. +CONFIG_BOARD_LATE_INIT=y
  13. +CONFIG_BOOTP_SEND_HOSTNAME=y
  14. +CONFIG_DEFAULT_ENV_FILE="linksys_e8450_env"
  15. +CONFIG_NR_DRAM_BANKS=1
  16. +CONFIG_DEBUG_UART_BASE=0x11002000
  17. +CONFIG_DEBUG_UART_CLOCK=25000000
  18. +CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi"
  19. +CONFIG_DEBUG_UART=y
  20. +CONFIG_SMBIOS_PRODUCT_NAME=""
  21. +CONFIG_AUTOBOOT_KEYED=y
  22. +CONFIG_BOOTDELAY=30
  23. +CONFIG_AUTOBOOT_MENU_SHOW=y
  24. +CONFIG_CFB_CONSOLE_ANSI=y
  25. +CONFIG_BUTTON=y
  26. +CONFIG_BUTTON_GPIO=y
  27. +CONFIG_GPIO_HOG=y
  28. +CONFIG_CMD_ENV_FLAGS=y
  29. +CONFIG_FIT=y
  30. +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
  31. +CONFIG_LED=y
  32. +CONFIG_LED_BLINK=y
  33. +CONFIG_LED_GPIO=y
  34. +CONFIG_LOGLEVEL=7
  35. +CONFIG_LOG=y
  36. +CONFIG_DEFAULT_FDT_FILE="mt7622-linksys-e8450"
  37. +CONFIG_SYS_PROMPT="MT7622> "
  38. +CONFIG_CMD_BOOTMENU=y
  39. +CONFIG_CMD_BOOTP=y
  40. +CONFIG_CMD_BUTTON=y
  41. +CONFIG_CMD_CDP=y
  42. +CONFIG_CMD_DHCP=y
  43. +CONFIG_CMD_DNS=y
  44. +CONFIG_CMD_ECHO=y
  45. +CONFIG_CMD_ENV_READMEM=y
  46. +CONFIG_CMD_ERASEENV=y
  47. +CONFIG_CMD_EXT4=y
  48. +CONFIG_CMD_FAT=y
  49. +CONFIG_CMD_FS_GENERIC=y
  50. +CONFIG_CMD_FS_UUID=y
  51. +CONFIG_CMD_GPIO=y
  52. +CONFIG_CMD_GPT=y
  53. +CONFIG_CMD_HASH=y
  54. +CONFIG_CMD_ITEST=y
  55. +CONFIG_CMD_LED=y
  56. +CONFIG_CMD_LICENSE=y
  57. +CONFIG_CMD_LINK_LOCAL=y
  58. +# CONFIG_CMD_MBR is not set
  59. +CONFIG_CMD_MTD=y
  60. +CONFIG_CMD_MTDPARTS=y
  61. +CONFIG_CMD_PCI=y
  62. +CONFIG_CMD_SF_TEST=y
  63. +CONFIG_CMD_PING=y
  64. +CONFIG_CMD_PXE=y
  65. +CONFIG_CMD_SMC=y
  66. +CONFIG_CMD_TFTPBOOT=y
  67. +CONFIG_CMD_TFTPSRV=y
  68. +CONFIG_CMD_UBI=y
  69. +CONFIG_CMD_UBI_RENAME=y
  70. +CONFIG_CMD_UBIFS=y
  71. +CONFIG_CMD_ASKENV=y
  72. +CONFIG_CMD_PART=y
  73. +CONFIG_CMD_PSTORE=y
  74. +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
  75. +CONFIG_CMD_RARP=y
  76. +CONFIG_CMD_SETEXPR=y
  77. +CONFIG_CMD_SLEEP=y
  78. +CONFIG_CMD_SNTP=y
  79. +CONFIG_CMD_SOURCE=y
  80. +CONFIG_CMD_USB=y
  81. +CONFIG_CMD_UUID=y
  82. +CONFIG_DISPLAY_CPUINFO=y
  83. +CONFIG_DM_REGULATOR=y
  84. +CONFIG_DM_REGULATOR_FIXED=y
  85. +CONFIG_DM_REGULATOR_GPIO=y
  86. +CONFIG_DM_USB=y
  87. +CONFIG_HUSH_PARSER=y
  88. +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  89. +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  90. +CONFIG_ENV_IS_IN_UBI=y
  91. +CONFIG_ENV_UBI_PART="ubi"
  92. +CONFIG_ENV_UBI_VOLUME="ubootenv"
  93. +CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
  94. +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  95. +CONFIG_VERSION_VARIABLE=y
  96. +CONFIG_PARTITION_UUIDS=y
  97. +CONFIG_NETCONSOLE=y
  98. +CONFIG_REGMAP=y
  99. +CONFIG_SYSCON=y
  100. +CONFIG_CLK=y
  101. +CONFIG_DM_MTD=y
  102. +CONFIG_DM_GPIO=y
  103. +CONFIG_PHY=y
  104. +CONFIG_PHY_MTK_TPHY=y
  105. +CONFIG_PHY_FIXED=y
  106. +CONFIG_DM_ETH=y
  107. +CONFIG_MEDIATEK_ETH=y
  108. +CONFIG_PCI=y
  109. +CONFIG_MTD=y
  110. +CONFIG_MTD_UBI_FASTMAP=y
  111. +CONFIG_DM_PCI=y
  112. +CONFIG_PCIE_MEDIATEK=y
  113. +CONFIG_PINCTRL=y
  114. +CONFIG_PINCONF=y
  115. +CONFIG_PINCTRL_MT7622=y
  116. +CONFIG_POWER_DOMAIN=y
  117. +CONFIG_PRE_CONSOLE_BUFFER=y
  118. +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
  119. +CONFIG_MTK_POWER_DOMAIN=y
  120. +CONFIG_RAM=y
  121. +CONFIG_DM_SERIAL=y
  122. +CONFIG_MTK_SERIAL=y
  123. +CONFIG_SPI=y
  124. +CONFIG_DM_SPI=y
  125. +CONFIG_MTK_SPI_NAND=y
  126. +CONFIG_MTK_SPI_NAND_MTD=y
  127. +CONFIG_SYSRESET_WATCHDOG=y
  128. +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  129. +CONFIG_WDT_MTK=y
  130. +CONFIG_LZO=y
  131. +CONFIG_ZSTD=y
  132. +CONFIG_HEXDUMP=y
  133. +CONFIG_RANDOM_UUID=y
  134. +CONFIG_REGEX=y
  135. +CONFIG_USE_IPADDR=y
  136. +CONFIG_IPADDR="192.168.1.1"
  137. +CONFIG_USE_SERVERIP=y
  138. +CONFIG_SERVERIP="192.168.1.254"
  139. +CONFIG_USB=y
  140. +CONFIG_USB_HOST=y
  141. +CONFIG_USB_XHCI_HCD=y
  142. +CONFIG_USB_XHCI_MTK=y
  143. +CONFIG_USB_STORAGE=y
  144. --- /dev/null
  145. +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts
  146. @@ -0,0 +1,214 @@
  147. +// SPDX-License-Identifier: GPL-2.0
  148. +/*
  149. + * Copyright (c) 2019 MediaTek Inc.
  150. + * Author: Sam Shih <[email protected]>
  151. + */
  152. +
  153. +/dts-v1/;
  154. +#include <dt-bindings/input/linux-event-codes.h>
  155. +#include "mt7622.dtsi"
  156. +#include "mt7622-u-boot.dtsi"
  157. +
  158. +/ {
  159. + #address-cells = <1>;
  160. + #size-cells = <1>;
  161. + model = "mt7622-linksys-e8450-ubi";
  162. + compatible = "mediatek,mt7622", "linksys,e8450-ubi";
  163. + chosen {
  164. + stdout-path = &uart0;
  165. + tick-timer = &timer0;
  166. + };
  167. +
  168. + aliases {
  169. + spi0 = &snand;
  170. + };
  171. +
  172. + gpio-keys {
  173. + compatible = "gpio-keys";
  174. +
  175. + factory {
  176. + label = "reset";
  177. + gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
  178. + linux,code = <KEY_RESTART>;
  179. + };
  180. +
  181. + wps {
  182. + label = "wps";
  183. + gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
  184. + linux,code = <KEY_WPS_BUTTON>;
  185. + };
  186. + };
  187. +
  188. + gpio-leds {
  189. + compatible = "gpio-leds";
  190. +
  191. + led_power: power_blue {
  192. + label = "power:blue";
  193. + gpios = <&gpio 95 GPIO_ACTIVE_LOW>;
  194. + default-state = "on";
  195. + };
  196. +
  197. + power_orange {
  198. + label = "power:orange";
  199. + gpios = <&gpio 96 GPIO_ACTIVE_LOW>;
  200. + default-state = "off";
  201. + };
  202. +
  203. + inet_blue {
  204. + label = "inet:blue";
  205. + gpios = <&gpio 97 GPIO_ACTIVE_LOW>;
  206. + default-state = "off";
  207. + };
  208. +
  209. + inet_orange {
  210. + label = "inet:orange";
  211. + gpios = <&gpio 98 GPIO_ACTIVE_LOW>;
  212. + default-state = "off";
  213. + };
  214. + };
  215. +
  216. + memory@40000000 {
  217. + device_type = "memory";
  218. + reg = <0x40000000 0x20000000>;
  219. + };
  220. +
  221. + reg_1p8v: regulator-1p8v {
  222. + compatible = "regulator-fixed";
  223. + regulator-name = "fixed-1.8V";
  224. + regulator-min-microvolt = <1800000>;
  225. + regulator-max-microvolt = <1800000>;
  226. + regulator-boot-on;
  227. + regulator-always-on;
  228. + };
  229. +
  230. + reg_3p3v: regulator-3p3v {
  231. + compatible = "regulator-fixed";
  232. + regulator-name = "fixed-3.3V";
  233. + regulator-min-microvolt = <3300000>;
  234. + regulator-max-microvolt = <3300000>;
  235. + regulator-boot-on;
  236. + regulator-always-on;
  237. + };
  238. +
  239. + reg_5v: regulator-5v {
  240. + compatible = "regulator-fixed";
  241. + regulator-name = "fixed-5V";
  242. + regulator-min-microvolt = <5000000>;
  243. + regulator-max-microvolt = <5000000>;
  244. + regulator-boot-on;
  245. + regulator-always-on;
  246. + };
  247. +};
  248. +
  249. +&pcie {
  250. + pinctrl-names = "default";
  251. + pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
  252. + status = "okay";
  253. +
  254. + pcie@0,0 {
  255. + status = "okay";
  256. + };
  257. +
  258. + pcie@1,0 {
  259. + status = "okay";
  260. + };
  261. +};
  262. +
  263. +&pinctrl {
  264. + pcie0_pins: pcie0-pins {
  265. + mux {
  266. + function = "pcie";
  267. + groups = "pcie0_pad_perst",
  268. + "pcie0_1_waken",
  269. + "pcie0_1_clkreq";
  270. + };
  271. + };
  272. +
  273. + pcie1_pins: pcie1-pins {
  274. + mux {
  275. + function = "pcie";
  276. + groups = "pcie1_pad_perst",
  277. + "pcie1_0_waken",
  278. + "pcie1_0_clkreq";
  279. + };
  280. + };
  281. +
  282. + snfi_pins: snfi-pins {
  283. + mux {
  284. + function = "flash";
  285. + groups = "snfi";
  286. + };
  287. + };
  288. +
  289. + uart0_pins: uart0 {
  290. + mux {
  291. + function = "uart";
  292. + groups = "uart0_0_tx_rx" ;
  293. + };
  294. + };
  295. +
  296. + watchdog_pins: watchdog-default {
  297. + mux {
  298. + function = "watchdog";
  299. + groups = "watchdog";
  300. + };
  301. + };
  302. +};
  303. +
  304. +&snand {
  305. + pinctrl-names = "default";
  306. + pinctrl-0 = <&snfi_pins>;
  307. + status = "okay";
  308. + quad-spi;
  309. +
  310. + partitions {
  311. + compatible = "fixed-partitions";
  312. + #address-cells = <1>;
  313. + #size-cells = <1>;
  314. +
  315. + partition@0 {
  316. + label = "bl2";
  317. + reg = <0x0 0x80000>;
  318. + };
  319. +
  320. + partition@80000 {
  321. + label = "ubi";
  322. + reg = <0x80000 0x7f80000>;
  323. + compatible = "linux,ubi";
  324. + };
  325. + };
  326. +};
  327. +
  328. +&uart0 {
  329. + mediatek,force-highspeed;
  330. + status = "okay";
  331. +};
  332. +
  333. +&watchdog {
  334. + pinctrl-names = "default";
  335. + pinctrl-0 = <&watchdog_pins>;
  336. + status = "okay";
  337. +};
  338. +
  339. +&eth {
  340. + status = "okay";
  341. + mediatek,gmac-id = <0>;
  342. + phy-mode = "2500base-x";
  343. + mediatek,switch = "mt7531";
  344. + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
  345. +
  346. + fixed-link {
  347. + speed = <2500>;
  348. + full-duplex;
  349. + };
  350. +};
  351. +
  352. +&ssusb {
  353. + vusb33-supply = <&reg_3p3v>;
  354. + vbus-supply = <&reg_5v>;
  355. + status = "okay";
  356. +};
  357. +
  358. +&u3phy {
  359. + status = "okay";
  360. +};
  361. --- a/arch/arm/dts/Makefile
  362. +++ b/arch/arm/dts/Makefile
  363. @@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  364. mt7622-rfb.dtb \
  365. mt7623a-unielec-u7623-02-emmc.dtb \
  366. mt7622-bananapi-bpi-r64.dtb \
  367. + mt7622-linksys-e8450-ubi.dtb \
  368. mt7623n-bananapi-bpi-r2.dtb \
  369. mt7629-rfb.dtb \
  370. mt7981-rfb.dtb \
  371. --- /dev/null
  372. +++ b/linksys_e8450_env
  373. @@ -0,0 +1,55 @@
  374. +ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory
  375. +ipaddr=192.168.1.1
  376. +serverip=192.168.1.254
  377. +loadaddr=0x48000000
  378. +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi
  379. +bootconf=config-1
  380. +bootdelay=0
  381. +bootfile=openwrt-mediatek-mt7622-linksys_e8450-ubi-initramfs-recovery.itb
  382. +bootfile_bl2=openwrt-mediatek-mt7622-linksys_e8450-ubi-preloader.bin
  383. +bootfile_fip=openwrt-mediatek-mt7622-linksys_e8450-ubi-bl31-uboot.fip
  384. +bootfile_upg=openwrt-mediatek-mt7622-linksys_e8450-ubi-squashfs-sysupgrade.itb
  385. +bootled_pwr=power:blue
  386. +bootled_rec=inet:orange on
  387. +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
  388. +bootmenu_default=0
  389. +bootmenu_delay=0
  390. +bootmenu_title= ( ( ( OpenWrt ) ) )
  391. +bootmenu_0=Initialize environment.=run _firstboot
  392. +bootmenu_0d=Run default boot command.=run boot_default
  393. +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
  394. +bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return
  395. +bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return
  396. +bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
  397. +bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
  398. +bootmenu_6=Load BL31+U-Boot FIP via TFTP then write to flash.=run boot_tftp_write_fip ; run bootmenu_confirm_return
  399. +bootmenu_7=Load BL2 preloader via TFTP then write to flash.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
  400. +bootmenu_8=Reboot.=reset
  401. +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
  402. +boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
  403. +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
  404. +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off
  405. +boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off
  406. +boot_serial_write_bl2=loadx $loadaddr 115200 && run snand_write_bl2
  407. +boot_serial_write_fip=loadx $loadaddr 115200 && run ubi_write_fip
  408. +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
  409. +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done
  410. +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
  411. +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi
  412. +boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
  413. +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip
  414. +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery
  415. +snand_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000
  416. +reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
  417. +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
  418. +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
  419. +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
  420. +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
  421. +ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000
  422. +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi
  423. +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi
  424. +_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic
  425. +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format
  426. +_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
  427. +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
  428. +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"