421-zbtlink_zbt-wg3526-16m.patch 8.5 KB

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  1. --- /dev/null
  2. +++ b/configs/mt7621_zbtlink_zbt-wg3526-16m_defconfig
  3. @@ -0,0 +1,138 @@
  4. +CONFIG_MIPS=y
  5. +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  6. +CONFIG_SYS_MALLOC_LEN=0x100000
  7. +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8. +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9. +CONFIG_NR_DRAM_BANKS=1
  10. +CONFIG_ENV_SIZE=0x1000
  11. +CONFIG_ENV_IS_IN_MTD=y
  12. +CONFIG_ENV_MTD_NAME="nor0"
  13. +CONFIG_ENV_SIZE_REDUND=0x10000
  14. +CONFIG_ENV_SIZE=0x10000
  15. +CONFIG_ENV_OFFSET=0x30000
  16. +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  17. +CONFIG_RESET_BUTTON_SETTLE_DELAY=400
  18. +CONFIG_BOOTP_SEND_HOSTNAME=y
  19. +# CONFIG_BOOTSTD is not set
  20. +CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env"
  21. +CONFIG_DEFAULT_DEVICE_TREE="zbtlink,zbt-wg3526"
  22. +CONFIG_SPL_BSS_MAX_SIZE=0x80000
  23. +CONFIG_SPL_BSS_START_ADDR=0x80140000
  24. +CONFIG_SPL_SERIAL=y
  25. +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
  26. +CONFIG_SPL=y
  27. +CONFIG_DEBUG_UART_BASE=0xbe000c00
  28. +CONFIG_DEBUG_UART_CLOCK=50000000
  29. +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
  30. +CONFIG_SYS_LOAD_ADDR=0x83000000
  31. +CONFIG_SYS_MIPS_TIMER_FREQ=440000000
  32. +CONFIG_ARCH_MTMIPS=y
  33. +CONFIG_SOC_MT7621=y
  34. +# CONFIG_MIPS_CACHE_SETUP is not set
  35. +# CONFIG_MIPS_CACHE_DISABLE is not set
  36. +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
  37. +CONFIG_MIPS_BOOT_FDT=y
  38. +CONFIG_DEBUG_UART=y
  39. +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
  40. +CONFIG_AUTOBOOT_KEYED=y
  41. +CONFIG_BOOTDELAY=30
  42. +CONFIG_AUTOBOOT_MENU_SHOW=y
  43. +CONFIG_CFB_CONSOLE_ANSI=y
  44. +CONFIG_BUTTON=y
  45. +CONFIG_BUTTON_GPIO=y
  46. +CONFIG_GPIO_HOG=y
  47. +CONFIG_CMD_ENV_FLAGS=y
  48. +CONFIG_FIT=y
  49. +# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set
  50. +CONFIG_HUSH_PARSER=y
  51. +CONFIG_LOGLEVEL=6
  52. +# CONFIG_LOG is not set
  53. +# CONFIG_SYS_LONGHELP is not set
  54. +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
  55. +CONFIG_SYS_CONSOLE_INFO_QUIET=y
  56. +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
  57. +CONFIG_SPL_NOR_SUPPORT=y
  58. +CONFIG_TPL=y
  59. +# CONFIG_TPL_FRAMEWORK is not set
  60. +CONFIG_LEGACY_IMAGE_FORMAT=y
  61. +# CONFIG_BOOTM_NETBSD is not set
  62. +# CONFIG_BOOTM_PLAN9 is not set
  63. +# CONFIG_BOOTM_RTEMS is not set
  64. +# CONFIG_BOOTM_VXWORKS is not set
  65. +# CONFIG_EFI is not set
  66. +# CONFIG_EFI_LOADER is not set
  67. +CONFIG_CMD_BOOTMENU=y
  68. +# CONFIG_CMD_BOOTEFI is not set
  69. +# CONFIG_CMD_BOOTD is not set
  70. +# CONFIG_CMD_BOOTP is not set
  71. +CONFIG_CMD_BOOTM=y
  72. +# CONFIG_CMD_BOOTDEV is not set
  73. +# CONFIG_CMD_BOOTFLOW is not set
  74. +CONFIG_CMD_BUTTON=y
  75. +CONFIG_CMD_ECHO=y
  76. +# CONFIG_CMD_ELF is not set
  77. +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
  78. +CONFIG_CMD_ENV_READMEM=y
  79. +CONFIG_CMD_ERASEENV=y
  80. +CONFIG_CMD_GPIO=y
  81. +CONFIG_CMD_HASH=y
  82. +CONFIG_CMD_ITEST=y
  83. +CONFIG_CMD_LED=y
  84. +# CONFIG_CMD_MBR is not set
  85. +CONFIG_CMD_MMC=y
  86. +CONFIG_CMD_MTD=y
  87. +CONFIG_CMD_MTDPART=y
  88. +# CONFIG_CMD_PCI is not set
  89. +CONFIG_CMD_SF_TEST=y
  90. +CONFIG_CMD_PING=y
  91. +CONFIG_CMD_TFTPBOOT=y
  92. +# CONFIG_CMD_UNLZ4 is not set
  93. +CONFIG_CMD_ASKENV=y
  94. +CONFIG_CMD_SETEXPR=y
  95. +CONFIG_CMD_SLEEP=y
  96. +CONFIG_CMD_SOURCE=y
  97. +CONFIG_DOS_PARTITION=y
  98. +# CONFIG_SPL_DOS_PARTITION is not set
  99. +# CONFIG_ISO_PARTITION is not set
  100. +# CONFIG_EFI_PARTITION is not set
  101. +# CONFIG_SPL_EFI_PARTITION is not set
  102. +CONFIG_PARTITION_TYPE_GUID=y
  103. +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  104. +# CONFIG_NET_RANDOM_ETHADDR is not set
  105. +# CONFIG_I2C is not set
  106. +# CONFIG_INPUT is not set
  107. +CONFIG_MMC=y
  108. +# CONFIG_MMC_QUIRKS is not set
  109. +# CONFIG_MMC_HW_PARTITIONING is not set
  110. +CONFIG_MMC_MTK=y
  111. +CONFIG_MTD=y
  112. +CONFIG_DM_MTD=y
  113. +CONFIG_SF_DEFAULT_SPEED=20000000
  114. +# CONFIG_SPI_FLASH_BAR is not set
  115. +# CONFIG_SPI_FLASH_EON is not set
  116. +# CONFIG_SPI_FLASH_GIGADEVICE is not set
  117. +# CONFIG_SPI_FLASH_ISSI is not set
  118. +# CONFIG_SPI_FLASH_MACRONIX is not set
  119. +# CONFIG_SPI_FLASH_SPANSION is not set
  120. +# CONFIG_SPI_FLASH_STMICRO is not set
  121. +CONFIG_SPI_FLASH_WINBOND=y
  122. +# CONFIG_SPI_FLASH_XMC is not set
  123. +# CONFIG_SPI_FLASH_XTX is not set
  124. +CONFIG_SPI_FLASH_MTD=y
  125. +CONFIG_MEDIATEK_ETH=y
  126. +CONFIG_PHY=y
  127. +CONFIG_PHY_MTK_TPHY=y
  128. +CONFIG_DEBUG_UART_SHIFT=2
  129. +CONFIG_SPI=y
  130. +CONFIG_MT7621_SPI=y
  131. +CONFIG_SYSRESET=y
  132. +CONFIG_SYSRESET_RESETCTL=y
  133. +# CONFIG_SYS_XTRACE is not set
  134. +CONFIG_USE_DEFAULT_ENV_FILE=y
  135. +CONFIG_VERSION_VARIABLE=y
  136. +CONFIG_WDT=y
  137. +CONFIG_WDT_MT7621=y
  138. +# CONFIG_BINMAN_FDT is not set
  139. +CONFIG_LZMA=y
  140. +CONFIG_SPL_LZMA=y
  141. +# CONFIG_GZIP is not set
  142. --- /dev/null
  143. +++ b/zbtlink_zbt-wg3526-16m_env
  144. @@ -0,0 +1,36 @@
  145. +ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory
  146. +ipaddr=192.168.1.1
  147. +serverip=192.168.1.254
  148. +loadaddr=0x83000000
  149. +bootcmd=run boot_nor
  150. +bootdelay=0
  151. +bootfile=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-initramfs-kernel.bin
  152. +bootfile_uboot=u-boot-mt7621.bin
  153. +bootfile_upg=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-squashfs-sysupgrade.bin
  154. +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
  155. +bootmenu_default=0
  156. +bootmenu_delay=0
  157. +bootmenu_title= ( ( ( OpenWrt ) ) )
  158. +bootmenu_0=Initialize environment.=run _firstboot
  159. +bootmenu_0d=Run default boot command.=run boot_default
  160. +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
  161. +bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return
  162. +bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return
  163. +bootmenu_4=Load U-Boot via TFTP then write to flash.=run boot_tftp_write_uboot ; run bootmenu_confirm_return
  164. +bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset
  165. +bootmenu_6=Reboot.=reset
  166. +boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
  167. +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever
  168. +boot_nor=bootm 0x1fc50000
  169. +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
  170. +boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done
  171. +boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production
  172. +boot_tftp_write_uboot=tftpboot $loadaddr $bootfile_uboot && run nor_write_uboot
  173. +reset_factory=mtd erase u-boot-env 0x0 0x10000 && reset
  174. +nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000
  175. +nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0xfb0000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize
  176. +nor_write_uboot=mtd erase u-boot 0x0 0x30000 && mtd write u-boot $loadaddr 0x0 0x30000
  177. +_init_env=setenv _init_env ; saveenv
  178. +_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
  179. +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
  180. +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title $ver"
  181. --- /dev/null
  182. +++ b/arch/mips/dts/zbtlink,zbt-wg3526.dts
  183. @@ -0,0 +1,131 @@
  184. +// SPDX-License-Identifier: GPL-2.0
  185. +/*
  186. + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
  187. + *
  188. + * Author: Weijie Gao <[email protected]>
  189. + */
  190. +
  191. +/dts-v1/;
  192. +
  193. +#include "mt7621.dtsi"
  194. +#include <dt-bindings/gpio/gpio.h>
  195. +
  196. +/ {
  197. + compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
  198. + model = "Zbtlink WG3526";
  199. +
  200. + aliases {
  201. + ethernet0 = &eth;
  202. + serial0 = &uart0;
  203. + spi0 = &spi;
  204. + };
  205. +
  206. + chosen {
  207. + stdout-path = &uart0;
  208. + };
  209. +
  210. + keys {
  211. + compatible = "gpio-keys";
  212. +
  213. + reset {
  214. + label = "reset";
  215. + gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
  216. + };
  217. + };
  218. +
  219. + leds {
  220. + compatible = "gpio-leds";
  221. +
  222. + led_status: status {
  223. + label = "green:status";
  224. + gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
  225. + };
  226. + };
  227. +};
  228. +
  229. +&pinctrl {
  230. + state_default: pin_state {
  231. + gpios {
  232. + groups = "i2c", "uart3", "pcie reset";
  233. + function = "gpio";
  234. + };
  235. +
  236. + wdt {
  237. + groups = "wdt";
  238. + function = "wdt rst";
  239. + };
  240. +
  241. + jtag {
  242. + groups = "jtag";
  243. + function = "jtag";
  244. + };
  245. + };
  246. +};
  247. +
  248. +&uart0 {
  249. + status = "okay";
  250. +};
  251. +
  252. +&gpio {
  253. + status = "okay";
  254. +};
  255. +
  256. +&spi {
  257. + status = "okay";
  258. + num-cs = <2>;
  259. +
  260. + spi-flash@0 {
  261. + #address-cells = <1>;
  262. + #size-cells = <1>;
  263. + compatible = "jedec,spi-nor";
  264. + spi-max-frequency = <25000000>;
  265. + reg = <0>;
  266. +
  267. +
  268. + partitions {
  269. + compatible = "fixed-partitions";
  270. + #address-cells = <1>;
  271. + #size-cells = <1>;
  272. +
  273. + partition@0 {
  274. + label = "u-boot";
  275. + reg = <0x0 0x30000>;
  276. + };
  277. +
  278. + partition@30000 {
  279. + label = "u-boot-env";
  280. + reg = <0x30000 0x10000>;
  281. + };
  282. +
  283. + factory: partition@40000 {
  284. + label = "factory";
  285. + reg = <0x40000 0x10000>;
  286. + read-only;
  287. + };
  288. +
  289. + firmware: partition@50000 {
  290. + compatible = "denx,uimage";
  291. + label = "firmware";
  292. + reg = <0x50000 0xfb0000>;
  293. + };
  294. + };
  295. + };
  296. +};
  297. +
  298. +&eth {
  299. + status = "okay";
  300. +};
  301. +
  302. +&mmc {
  303. + cap-sd-highspeed;
  304. +
  305. + status = "okay";
  306. +};
  307. +
  308. +&ssusb {
  309. + status = "okay";
  310. +};
  311. +
  312. +&u3phy {
  313. + status = "okay";
  314. +};