mt7620a.dtsi 10 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mt7620a-soc";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu@0 {
  9. compatible = "mips,mips24KEc";
  10. reg = <0>;
  11. };
  12. };
  13. chosen {
  14. bootargs = "console=ttyS0,57600";
  15. };
  16. cpuintc: cpuintc {
  17. #address-cells = <0>;
  18. #interrupt-cells = <1>;
  19. interrupt-controller;
  20. compatible = "mti,cpu-interrupt-controller";
  21. };
  22. aliases {
  23. spi0 = &spi0;
  24. spi1 = &spi1;
  25. serial0 = &uartlite;
  26. };
  27. palmbus: palmbus@10000000 {
  28. compatible = "palmbus";
  29. reg = <0x10000000 0x200000>;
  30. ranges = <0x0 0x10000000 0x1FFFFF>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. sysc: sysc@0 {
  34. compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
  35. reg = <0x0 0x100>;
  36. };
  37. timer: timer@100 {
  38. compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
  39. reg = <0x100 0x20>;
  40. interrupt-parent = <&intc>;
  41. interrupts = <1>;
  42. };
  43. watchdog: watchdog@120 {
  44. compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
  45. reg = <0x120 0x10>;
  46. resets = <&rstctrl 8>;
  47. reset-names = "wdt";
  48. interrupt-parent = <&intc>;
  49. interrupts = <1>;
  50. };
  51. intc: intc@200 {
  52. compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
  53. reg = <0x200 0x100>;
  54. resets = <&rstctrl 19>;
  55. reset-names = "intc";
  56. interrupt-controller;
  57. #interrupt-cells = <1>;
  58. interrupt-parent = <&cpuintc>;
  59. interrupts = <2>;
  60. };
  61. memc: memc@300 {
  62. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  63. reg = <0x300 0x100>;
  64. resets = <&rstctrl 20>;
  65. reset-names = "mc";
  66. interrupt-parent = <&intc>;
  67. interrupts = <3>;
  68. };
  69. uart: uart@500 {
  70. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  71. reg = <0x500 0x100>;
  72. resets = <&rstctrl 12>;
  73. reset-names = "uart";
  74. interrupt-parent = <&intc>;
  75. interrupts = <5>;
  76. reg-shift = <2>;
  77. status = "disabled";
  78. };
  79. gpio0: gpio@600 {
  80. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  81. reg = <0x600 0x34>;
  82. resets = <&rstctrl 13>;
  83. reset-names = "pio";
  84. interrupt-parent = <&intc>;
  85. interrupts = <6>;
  86. gpio-controller;
  87. #gpio-cells = <2>;
  88. ralink,gpio-base = <0>;
  89. ralink,nr-gpio = <24>;
  90. ralink,register-map = [ 00 04 08 0c
  91. 20 24 28 2c
  92. 30 34 ];
  93. };
  94. gpio1: gpio@638 {
  95. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  96. reg = <0x638 0x24>;
  97. interrupt-parent = <&intc>;
  98. interrupts = <6>;
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. ralink,gpio-base = <24>;
  102. ralink,nr-gpio = <16>;
  103. ralink,register-map = [ 00 04 08 0c
  104. 10 14 18 1c
  105. 20 24 ];
  106. status = "disabled";
  107. };
  108. gpio2: gpio@660 {
  109. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  110. reg = <0x660 0x24>;
  111. interrupt-parent = <&intc>;
  112. interrupts = <6>;
  113. gpio-controller;
  114. #gpio-cells = <2>;
  115. ralink,gpio-base = <40>;
  116. ralink,nr-gpio = <32>;
  117. ralink,register-map = [ 00 04 08 0c
  118. 10 14 18 1c
  119. 20 24 ];
  120. status = "disabled";
  121. };
  122. gpio3: gpio@688 {
  123. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  124. reg = <0x688 0x24>;
  125. interrupt-parent = <&intc>;
  126. interrupts = <6>;
  127. gpio-controller;
  128. #gpio-cells = <2>;
  129. ralink,gpio-base = <72>;
  130. ralink,nr-gpio = <1>;
  131. ralink,register-map = [ 00 04 08 0c
  132. 10 14 18 1c
  133. 20 24 ];
  134. status = "disabled";
  135. };
  136. i2c: i2c@900 {
  137. compatible = "ralink,rt2880-i2c";
  138. reg = <0x900 0x100>;
  139. resets = <&rstctrl 16>;
  140. reset-names = "i2c";
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. status = "disabled";
  144. pinctrl-names = "default";
  145. pinctrl-0 = <&i2c_pins>;
  146. };
  147. i2s: i2s@a00 {
  148. compatible = "mediatek,mt7620-i2s";
  149. reg = <0xa00 0x100>;
  150. resets = <&rstctrl 17>;
  151. reset-names = "i2s";
  152. interrupt-parent = <&intc>;
  153. interrupts = <10>;
  154. txdma-req = <2>;
  155. rxdma-req = <3>;
  156. dmas = <&gdma 4>,
  157. <&gdma 6>;
  158. dma-names = "tx", "rx";
  159. status = "disabled";
  160. };
  161. spi0: spi@b00 {
  162. compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
  163. reg = <0xb00 0x40>;
  164. resets = <&rstctrl 18>;
  165. reset-names = "spi";
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. status = "disabled";
  169. pinctrl-names = "default";
  170. pinctrl-0 = <&spi_pins>;
  171. };
  172. spi1: spi@b40 {
  173. compatible = "ralink,rt2880-spi";
  174. reg = <0xb40 0x60>;
  175. resets = <&rstctrl 18>;
  176. reset-names = "spi";
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. status = "disabled";
  180. pinctrl-names = "default";
  181. pinctrl-0 = <&spi_cs1>;
  182. };
  183. uartlite: uartlite@c00 {
  184. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  185. reg = <0xc00 0x100>;
  186. resets = <&rstctrl 19>;
  187. reset-names = "uartl";
  188. interrupt-parent = <&intc>;
  189. interrupts = <12>;
  190. reg-shift = <2>;
  191. pinctrl-names = "default";
  192. pinctrl-0 = <&uartlite_pins>;
  193. };
  194. systick: systick@d00 {
  195. compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
  196. reg = <0xd00 0x10>;
  197. resets = <&rstctrl 28>;
  198. reset-names = "intc";
  199. interrupt-parent = <&cpuintc>;
  200. interrupts = <7>;
  201. };
  202. pcm: pcm@2000 {
  203. compatible = "ralink,mt7620a-pcm";
  204. reg = <0x2000 0x800>;
  205. resets = <&rstctrl 11>;
  206. reset-names = "pcm";
  207. interrupt-parent = <&intc>;
  208. interrupts = <4>;
  209. status = "disabled";
  210. };
  211. gdma: gdma@2800 {
  212. compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
  213. reg = <0x2800 0x800>;
  214. resets = <&rstctrl 14>;
  215. reset-names = "dma";
  216. interrupt-parent = <&intc>;
  217. interrupts = <7>;
  218. #dma-cells = <1>;
  219. #dma-channels = <16>;
  220. #dma-requests = <16>;
  221. status = "disabled";
  222. };
  223. };
  224. pinctrl: pinctrl {
  225. compatible = "ralink,rt2880-pinmux";
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&state_default>;
  228. state_default: pinctrl0 {
  229. };
  230. pcm_i2s_pins: pcm_i2s {
  231. pcm_i2s {
  232. ralink,group = "uartf";
  233. ralink,function = "pcm i2s";
  234. };
  235. };
  236. uartf_gpio_pins: uartf_gpio {
  237. uartf_gpio {
  238. ralink,group = "uartf";
  239. ralink,function = "gpio uartf";
  240. };
  241. };
  242. gpio_i2s_pins: gpio_i2s {
  243. gpio_i2s {
  244. ralink,group = "uartf";
  245. ralink,function = "gpio i2s";
  246. };
  247. };
  248. spi_pins: spi {
  249. spi {
  250. ralink,group = "spi";
  251. ralink,function = "spi";
  252. };
  253. };
  254. spi_cs1: spi1 {
  255. spi1 {
  256. ralink,group = "spi refclk";
  257. ralink,function = "spi refclk";
  258. };
  259. };
  260. i2c_pins: i2c {
  261. i2c {
  262. ralink,group = "i2c";
  263. ralink,function = "i2c";
  264. };
  265. };
  266. uartlite_pins: uartlite {
  267. uart {
  268. ralink,group = "uartlite";
  269. ralink,function = "uartlite";
  270. };
  271. };
  272. mdio_pins: mdio {
  273. mdio {
  274. ralink,group = "mdio";
  275. ralink,function = "mdio";
  276. };
  277. };
  278. mdio_refclk_pins: mdio_refclk {
  279. mdio_refclk {
  280. ralink,group = "mdio";
  281. ralink,function = "refclk";
  282. };
  283. };
  284. ephy_pins: ephy {
  285. ephy {
  286. ralink,group = "ephy";
  287. ralink,function = "ephy";
  288. };
  289. };
  290. wled_pins: wled {
  291. wled {
  292. ralink,group = "wled";
  293. ralink,function = "wled";
  294. };
  295. };
  296. rgmii1_pins: rgmii1 {
  297. rgmii1 {
  298. ralink,group = "rgmii1";
  299. ralink,function = "rgmii1";
  300. };
  301. };
  302. rgmii2_pins: rgmii2 {
  303. rgmii2 {
  304. ralink,group = "rgmii2";
  305. ralink,function = "rgmii2";
  306. };
  307. };
  308. pcie_pins: pcie {
  309. pcie {
  310. ralink,group = "pcie";
  311. ralink,function = "pcie rst";
  312. };
  313. };
  314. pa_pins: pa {
  315. pa {
  316. ralink,group = "pa";
  317. ralink,function = "pa";
  318. };
  319. };
  320. sdhci_pins: sdhci {
  321. sdhci {
  322. ralink,group = "nd_sd";
  323. ralink,function = "sd";
  324. };
  325. };
  326. };
  327. rstctrl: rstctrl {
  328. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  329. #reset-cells = <1>;
  330. };
  331. clkctrl: clkctrl {
  332. compatible = "ralink,rt2880-clock";
  333. #clock-cells = <1>;
  334. };
  335. usbphy: usbphy {
  336. compatible = "mediatek,mt7620-usbphy";
  337. #phy-cells = <0>;
  338. ralink,sysctl = <&sysc>;
  339. resets = <&rstctrl 22 &rstctrl 25>;
  340. reset-names = "host", "device";
  341. clocks = <&clkctrl 22 &clkctrl 25>;
  342. clock-names = "host", "device";
  343. };
  344. ethernet: ethernet@10100000 {
  345. compatible = "mediatek,mt7620-eth";
  346. reg = <0x10100000 0x10000>;
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. interrupt-parent = <&cpuintc>;
  350. interrupts = <5>;
  351. resets = <&rstctrl 21 &rstctrl 23>;
  352. reset-names = "fe", "esw";
  353. mediatek,switch = <&gsw>;
  354. port@4 {
  355. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  356. reg = <4>;
  357. status = "disabled";
  358. };
  359. port@5 {
  360. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  361. reg = <5>;
  362. status = "disabled";
  363. };
  364. mdio-bus {
  365. #address-cells = <1>;
  366. #size-cells = <0>;
  367. status = "disabled";
  368. };
  369. };
  370. gsw: gsw@10110000 {
  371. compatible = "mediatek,mt7620-gsw";
  372. reg = <0x10110000 0x8000>;
  373. resets = <&rstctrl 23>;
  374. reset-names = "esw";
  375. interrupt-parent = <&intc>;
  376. interrupts = <17>;
  377. };
  378. sdhci: sdhci@10130000 {
  379. compatible = "ralink,mt7620-sdhci";
  380. reg = <0x10130000 0x4000>;
  381. interrupt-parent = <&intc>;
  382. interrupts = <14>;
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&sdhci_pins>;
  385. status = "disabled";
  386. };
  387. ehci: ehci@101c0000 {
  388. compatible = "generic-ehci";
  389. reg = <0x101c0000 0x1000>;
  390. interrupt-parent = <&intc>;
  391. interrupts = <18>;
  392. phys = <&usbphy>;
  393. phy-names = "usb";
  394. status = "disabled";
  395. };
  396. ohci: ohci@101c1000 {
  397. compatible = "generic-ohci";
  398. reg = <0x101c1000 0x1000>;
  399. interrupt-parent = <&intc>;
  400. interrupts = <18>;
  401. phys = <&usbphy>;
  402. phy-names = "usb";
  403. status = "disabled";
  404. };
  405. pcie: pcie@10140000 {
  406. compatible = "mediatek,mt7620-pci";
  407. reg = <0x10140000 0x100
  408. 0x10142000 0x100>;
  409. #address-cells = <3>;
  410. #size-cells = <2>;
  411. resets = <&rstctrl 26>;
  412. reset-names = "pcie0";
  413. clocks = <&clkctrl 26>;
  414. clock-names = "pcie0";
  415. interrupt-parent = <&cpuintc>;
  416. interrupts = <4>;
  417. pinctrl-names = "default";
  418. pinctrl-0 = <&pcie_pins>;
  419. device_type = "pci";
  420. bus-range = <0 255>;
  421. ranges = <
  422. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  423. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  424. >;
  425. status = "disabled";
  426. pcie0: pcie@0,0 {
  427. reg = <0x0000 0 0 0 0>;
  428. #address-cells = <3>;
  429. #size-cells = <2>;
  430. device_type = "pci";
  431. ranges;
  432. };
  433. };
  434. wmac: wmac@10180000 {
  435. compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
  436. reg = <0x10180000 0x40000>;
  437. interrupt-parent = <&cpuintc>;
  438. interrupts = <6>;
  439. ralink,eeprom = "soc_wmac.eeprom";
  440. };
  441. };