qcom-ipq4019-cm520-79f.dts 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "MobiPromo CM520-79F";
  8. compatible = "mobipromo,cm520-79f";
  9. aliases {
  10. led-boot = &led_sys;
  11. led-failsafe = &led_sys;
  12. led-running = &led_sys;
  13. led-upgrade = &led_sys;
  14. };
  15. soc {
  16. rng@22000 {
  17. status = "okay";
  18. };
  19. mdio@90000 {
  20. status = "okay";
  21. pinctrl-0 = <&mdio_pins>;
  22. pinctrl-names = "default";
  23. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  24. reset-delay-us = <1000>;
  25. };
  26. tcsr@1949000 {
  27. compatible = "qcom,tcsr";
  28. reg = <0x1949000 0x100>;
  29. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  30. };
  31. tcsr@194b000 {
  32. compatible = "qcom,tcsr";
  33. reg = <0x194b000 0x100>;
  34. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  35. };
  36. ess_tcsr@1953000 {
  37. compatible = "qcom,tcsr";
  38. reg = <0x1953000 0x1000>;
  39. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  40. };
  41. tcsr@1957000 {
  42. compatible = "qcom,tcsr";
  43. reg = <0x1957000 0x100>;
  44. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  45. };
  46. usb2@60f8800 {
  47. status = "okay";
  48. dwc3@6000000 {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. usb2_port1: port@1 {
  52. reg = <1>;
  53. #trigger-source-cells = <0>;
  54. };
  55. };
  56. };
  57. usb3@8af8800 {
  58. status = "okay";
  59. dwc3@8a00000 {
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. usb3_port1: port@1 {
  63. reg = <1>;
  64. #trigger-source-cells = <0>;
  65. };
  66. usb3_port2: port@2 {
  67. reg = <2>;
  68. #trigger-source-cells = <0>;
  69. };
  70. };
  71. };
  72. crypto@8e3a000 {
  73. status = "okay";
  74. };
  75. watchdog@b017000 {
  76. status = "okay";
  77. };
  78. };
  79. led_spi {
  80. compatible = "spi-gpio";
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  84. mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
  85. num-chipselects = <0>;
  86. led_gpio: led_gpio@0 {
  87. compatible = "fairchild,74hc595";
  88. reg = <0>;
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. registers-number = <1>;
  92. spi-max-frequency = <1000000>;
  93. };
  94. };
  95. leds {
  96. compatible = "gpio-leds";
  97. usb {
  98. label = "blue:usb";
  99. gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
  100. linux,default-trigger = "usbport";
  101. trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
  102. };
  103. led_sys: can {
  104. label = "blue:can";
  105. gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
  106. };
  107. wan {
  108. label = "blue:wan";
  109. gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
  110. };
  111. lan1 {
  112. label = "blue:lan1";
  113. gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
  114. };
  115. lan2 {
  116. label = "blue:lan2";
  117. gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
  118. };
  119. wlan2g {
  120. label = "blue:wlan2g";
  121. gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
  122. linux,default-trigger = "phy0tpt";
  123. };
  124. wlan5g {
  125. label = "blue:wlan5g";
  126. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  127. linux,default-trigger = "phy1tpt";
  128. };
  129. };
  130. keys {
  131. compatible = "gpio-keys";
  132. reset {
  133. label = "reset";
  134. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  135. linux,code = <KEY_RESTART>;
  136. };
  137. };
  138. };
  139. &blsp_dma {
  140. status = "okay";
  141. };
  142. &blsp1_uart1 {
  143. status = "okay";
  144. };
  145. &blsp1_uart2 {
  146. status = "okay";
  147. };
  148. &cryptobam {
  149. status = "okay";
  150. };
  151. &nand {
  152. pinctrl-0 = <&nand_pins>;
  153. pinctrl-names = "default";
  154. status = "okay";
  155. nand@0 {
  156. partitions {
  157. compatible = "fixed-partitions";
  158. #address-cells = <1>;
  159. #size-cells = <1>;
  160. partition@0 {
  161. label = "SBL1";
  162. reg = <0x0 0x100000>;
  163. read-only;
  164. };
  165. partition@100000 {
  166. label = "MIBIB";
  167. reg = <0x100000 0x100000>;
  168. read-only;
  169. };
  170. partition@200000 {
  171. label = "BOOTCONFIG";
  172. reg = <0x200000 0x100000>;
  173. };
  174. partition@300000 {
  175. label = "QSEE";
  176. reg = <0x300000 0x100000>;
  177. read-only;
  178. };
  179. partition@400000 {
  180. label = "QSEE_1";
  181. reg = <0x400000 0x100000>;
  182. read-only;
  183. };
  184. partition@500000 {
  185. label = "CDT";
  186. reg = <0x500000 0x80000>;
  187. read-only;
  188. };
  189. partition@580000 {
  190. label = "CDT_1";
  191. reg = <0x580000 0x80000>;
  192. read-only;
  193. };
  194. partition@600000 {
  195. label = "BOOTCONFIG1";
  196. reg = <0x600000 0x80000>;
  197. };
  198. partition@680000 {
  199. label = "APPSBLENV";
  200. reg = <0x680000 0x80000>;
  201. };
  202. partition@700000 {
  203. label = "APPSBL";
  204. reg = <0x700000 0x200000>;
  205. read-only;
  206. };
  207. partition@900000 {
  208. label = "APPSBL_1";
  209. reg = <0x900000 0x200000>;
  210. read-only;
  211. };
  212. art: partition@b00000 {
  213. label = "ART";
  214. reg = <0xb00000 0x80000>;
  215. read-only;
  216. compatible = "nvmem-cells";
  217. #address-cells = <1>;
  218. #size-cells = <1>;
  219. precal_art_1000: precal@1000 {
  220. reg = <0x1000 0x2f20>;
  221. };
  222. macaddr_art_1006: macaddr@1006 {
  223. reg = <0x1006 0x6>;
  224. };
  225. precal_art_5000: precal@5000 {
  226. reg = <0x5000 0x2f20>;
  227. };
  228. macaddr_art_5006: macaddr@5006 {
  229. reg = <0x5006 0x6>;
  230. };
  231. };
  232. partition@b80000 {
  233. label = "ubi";
  234. reg = <0xb80000 0x7480000>;
  235. };
  236. };
  237. };
  238. };
  239. &qpic_bam {
  240. status = "okay";
  241. };
  242. &tlmm {
  243. mdio_pins: mdio_pinmux {
  244. mux_1 {
  245. pins = "gpio6";
  246. function = "mdio";
  247. bias-pull-up;
  248. };
  249. mux_2 {
  250. pins = "gpio7";
  251. function = "mdc";
  252. bias-pull-up;
  253. };
  254. };
  255. nand_pins: nand_pins {
  256. pullups {
  257. pins = "gpio52", "gpio53", "gpio58",
  258. "gpio59";
  259. function = "qpic";
  260. bias-pull-up;
  261. };
  262. pulldowns {
  263. pins = "gpio54", "gpio55", "gpio56",
  264. "gpio57", "gpio60", "gpio61",
  265. "gpio62", "gpio63", "gpio64",
  266. "gpio65", "gpio66", "gpio67",
  267. "gpio68", "gpio69";
  268. function = "qpic";
  269. bias-pull-down;
  270. };
  271. };
  272. };
  273. &usb3_ss_phy {
  274. status = "okay";
  275. };
  276. &usb3_hs_phy {
  277. status = "okay";
  278. };
  279. &usb2_hs_phy {
  280. status = "okay";
  281. };
  282. &gmac {
  283. status = "okay";
  284. nvmem-cells = <&macaddr_art_1006>;
  285. nvmem-cell-names = "mac-address";
  286. };
  287. &switch {
  288. status = "okay";
  289. };
  290. &swport3 {
  291. status = "okay";
  292. label = "lan2";
  293. };
  294. &swport4 {
  295. status = "okay";
  296. label = "lan1";
  297. };
  298. &swport5 {
  299. status = "okay";
  300. nvmem-cells = <&macaddr_art_5006>;
  301. nvmem-cell-names = "mac-address";
  302. };
  303. &wifi0 {
  304. status = "okay";
  305. nvmem-cell-names = "pre-calibration";
  306. nvmem-cells = <&precal_art_1000>;
  307. qcom,ath10k-calibration-variant = "CM520-79F";
  308. };
  309. &wifi1 {
  310. status = "okay";
  311. nvmem-cell-names = "pre-calibration";
  312. nvmem-cells = <&precal_art_5000>;
  313. qcom,ath10k-calibration-variant = "CM520-79F";
  314. };