qcom-ipq8065-tr4400-v2.dts 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. #include "qcom-ipq8065-smb208.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. / {
  6. model = "Arris TR4400 v2";
  7. compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
  8. memory@0 {
  9. reg = <0x42000000 0x1e000000>;
  10. device_type = "memory";
  11. };
  12. aliases {
  13. led-boot = &led_status_blue;
  14. led-failsafe = &led_status_red;
  15. led-running = &led_status_blue;
  16. led-upgrade = &led_status_red;
  17. };
  18. chosen {
  19. bootargs = "rootfstype=squashfs noinitrd";
  20. };
  21. keys {
  22. compatible = "gpio-keys";
  23. pinctrl-0 = <&button_pins>;
  24. pinctrl-names = "default";
  25. reset {
  26. label = "reset";
  27. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  28. linux,code = <KEY_RESTART>;
  29. debounce-interval = <60>;
  30. wakeup-source;
  31. };
  32. wps {
  33. label = "wps";
  34. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_WPS_BUTTON>;
  36. debounce-interval = <60>;
  37. wakeup-source;
  38. };
  39. };
  40. leds {
  41. compatible = "gpio-leds";
  42. pinctrl-0 = <&led_pins>;
  43. pinctrl-names = "default";
  44. led_status_red: status_red {
  45. function = LED_FUNCTION_STATUS;
  46. color = <LED_COLOR_ID_RED>;
  47. gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
  48. };
  49. led_status_blue: status_blue {
  50. function = LED_FUNCTION_STATUS;
  51. color = <LED_COLOR_ID_BLUE>;
  52. gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
  53. };
  54. };
  55. };
  56. &qcom_pinmux {
  57. button_pins: button_pins {
  58. mux {
  59. pins = "gpio6", "gpio54";
  60. function = "gpio";
  61. drive-strength = <2>;
  62. bias-pull-up;
  63. };
  64. };
  65. led_pins: led_pins {
  66. mux {
  67. pins = "gpio7", "gpio8";
  68. function = "gpio";
  69. drive-strength = <2>;
  70. bias-pull-down;
  71. };
  72. };
  73. rgmii2_pins: rgmii2-pins {
  74. tx {
  75. pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  76. input-disable;
  77. };
  78. };
  79. spi_pins: spi_pins {
  80. cs {
  81. pins = "gpio20";
  82. drive-strength = <12>;
  83. };
  84. };
  85. };
  86. &gsbi5 {
  87. qcom,mode = <GSBI_PROT_SPI>;
  88. status = "okay";
  89. spi@1a280000 {
  90. status = "okay";
  91. pinctrl-0 = <&spi_pins>;
  92. pinctrl-names = "default";
  93. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  94. flash@0 {
  95. compatible = "everspin,mr25h256";
  96. spi-max-frequency = <40000000>;
  97. reg = <0>;
  98. };
  99. };
  100. };
  101. &nand {
  102. status = "okay";
  103. nand@0 {
  104. reg = <0>;
  105. compatible = "qcom,nandcs";
  106. nand-ecc-strength = <4>;
  107. nand-bus-width = <8>;
  108. nand-ecc-step-size = <512>;
  109. qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
  110. partitions {
  111. compatible = "fixed-partitions";
  112. #address-cells = <1>;
  113. #size-cells = <1>;
  114. partition@0 {
  115. label = "0:SBL1";
  116. reg = <0x0000000 0x0040000>;
  117. read-only;
  118. };
  119. partition@40000 {
  120. label = "0:MIBIB";
  121. reg = <0x0040000 0x0140000>;
  122. read-only;
  123. };
  124. partition@180000 {
  125. label = "0:SBL2";
  126. reg = <0x0180000 0x0140000>;
  127. read-only;
  128. };
  129. partition@2c0000 {
  130. label = "0:SBL3";
  131. reg = <0x02c0000 0x0280000>;
  132. read-only;
  133. };
  134. partition@540000 {
  135. label = "0:DDRCONFIG";
  136. reg = <0x0540000 0x0120000>;
  137. read-only;
  138. };
  139. partition@660000 {
  140. label = "0:SSD";
  141. reg = <0x0660000 0x0120000>;
  142. read-only;
  143. };
  144. partition@780000 {
  145. label = "0:TZ";
  146. reg = <0x0780000 0x0280000>;
  147. read-only;
  148. };
  149. partition@a00000 {
  150. label = "0:RPM";
  151. reg = <0x0a00000 0x0280000>;
  152. read-only;
  153. };
  154. partition@c80000 {
  155. label = "0:APPSBL";
  156. reg = <0x0c80000 0x0500000>;
  157. read-only;
  158. };
  159. partition@1180000 {
  160. label = "0:APPSBLENV";
  161. reg = <0x1180000 0x0080000>;
  162. };
  163. partition@1200000 {
  164. label = "0:ART";
  165. reg = <0x1200000 0x0140000>;
  166. read-only;
  167. nvmem-layout {
  168. compatible = "fixed-layout";
  169. #address-cells = <1>;
  170. #size-cells = <1>;
  171. precal_ART_1000: precal@1000 {
  172. reg = <0x1000 0x2f20>;
  173. };
  174. precal_ART_5000: precal@5000 {
  175. reg = <0x5000 0x2f20>;
  176. };
  177. };
  178. };
  179. partition@1340000 {
  180. label = "extra";
  181. reg = <0x1340000 0x4000000>;
  182. };
  183. partition@5340000 {
  184. label = "0:BOOTCONFIG";
  185. reg = <0x5340000 0x0060000>;
  186. read-only;
  187. };
  188. partition@53a0000 {
  189. label = "0:SBL2_1";
  190. reg = <0x53a0000 0x0140000>;
  191. read-only;
  192. };
  193. partition@54e0000 {
  194. label = "0:SBL3_1";
  195. reg = <0x54e0000 0x0280000>;
  196. read-only;
  197. };
  198. partition@5760000 {
  199. label = "0:DDRCONFIG_1";
  200. reg = <0x5760000 0x0120000>;
  201. read-only;
  202. };
  203. partition@5880000 {
  204. label = "0:SSD_1";
  205. reg = <0x5880000 0x0120000>;
  206. read-only;
  207. };
  208. partition@59a0000 {
  209. label = "0:TZ_1";
  210. reg = <0x59a0000 0x0280000>;
  211. read-only;
  212. };
  213. partition@5c20000 {
  214. label = "0:RPM_1";
  215. reg = <0x5c20000 0x0280000>;
  216. read-only;
  217. };
  218. partition@5ea0000 {
  219. label = "0:BOOTCONFIG1";
  220. reg = <0x5ea0000 0x0060000>;
  221. read-only;
  222. };
  223. partition@5f00000 {
  224. label = "0:APPSBL_1";
  225. reg = <0x5f00000 0x0500000>;
  226. read-only;
  227. };
  228. partition@6400000 {
  229. label = "fw_env";
  230. reg = <0x6400000 0x0100000>;
  231. read-only;
  232. nvmem-layout {
  233. compatible = "fixed-layout";
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. macaddr_fw_env_0: macaddr@0 {
  237. reg = <0x00 0x6>;
  238. };
  239. macaddr_fw_env_6: macaddr@6 {
  240. reg = <0x06 0x6>;
  241. };
  242. macaddr_fw_env_c: macaddr@c {
  243. reg = <0x0c 0x6>;
  244. };
  245. macaddr_fw_env_12: macaddr@12 {
  246. reg = <0x12 0x6>;
  247. };
  248. macaddr_fw_env_18: macaddr@18 {
  249. reg = <0x18 0x6>;
  250. };
  251. };
  252. };
  253. partition@6500000 {
  254. label = "ubi";
  255. reg = <0x6500000 0x9b00000>;
  256. };
  257. };
  258. };
  259. };
  260. &mdio0 {
  261. status = "okay";
  262. pinctrl-0 = <&mdio0_pins>;
  263. pinctrl-names = "default";
  264. switch@10 {
  265. compatible = "qca,qca8337";
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. reg = <0x10>;
  269. ports {
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. port@0 {
  273. reg = <0>;
  274. label = "cpu";
  275. ethernet = <&gmac0>;
  276. phy-mode = "rgmii";
  277. tx-internal-delay-ps = <1000>;
  278. rx-internal-delay-ps = <1000>;
  279. fixed-link {
  280. speed = <1000>;
  281. full-duplex;
  282. };
  283. };
  284. port@1 {
  285. reg = <1>;
  286. label = "lan1";
  287. phy-mode = "internal";
  288. phy-handle = <&phy_port1>;
  289. };
  290. port@2 {
  291. reg = <2>;
  292. label = "lan2";
  293. phy-mode = "internal";
  294. phy-handle = <&phy_port2>;
  295. };
  296. port@3 {
  297. reg = <3>;
  298. label = "lan3";
  299. phy-mode = "internal";
  300. phy-handle = <&phy_port3>;
  301. };
  302. port@4 {
  303. reg = <4>;
  304. label = "lan4";
  305. phy-mode = "internal";
  306. phy-handle = <&phy_port4>;
  307. };
  308. port@6 {
  309. reg = <6>;
  310. label = "cpu";
  311. ethernet = <&gmac1>;
  312. phy-mode = "sgmii";
  313. qca,sgmii-enable-pll;
  314. fixed-link {
  315. speed = <1000>;
  316. full-duplex;
  317. };
  318. };
  319. };
  320. mdio {
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. phy_port1: phy@0 {
  324. reg = <0>;
  325. };
  326. phy_port2: phy@1 {
  327. reg = <1>;
  328. };
  329. phy_port3: phy@2 {
  330. reg = <2>;
  331. };
  332. phy_port4: phy@3 {
  333. reg = <3>;
  334. };
  335. };
  336. };
  337. phy7: ethernet-phy@7 {
  338. reg = <7>;
  339. };
  340. };
  341. &gmac0 {
  342. status = "okay";
  343. phy-mode = "rgmii";
  344. qcom,id = <0>;
  345. nvmem-cells = <&macaddr_fw_env_18>;
  346. nvmem-cell-names = "mac-address";
  347. pinctrl-0 = <&rgmii2_pins>;
  348. pinctrl-names = "default";
  349. fixed-link {
  350. speed = <1000>;
  351. full-duplex;
  352. };
  353. };
  354. &gmac1 {
  355. status = "okay";
  356. phy-mode = "sgmii";
  357. qcom,id = <1>;
  358. nvmem-cells = <&macaddr_fw_env_0>;
  359. nvmem-cell-names = "mac-address";
  360. fixed-link {
  361. speed = <1000>;
  362. full-duplex;
  363. };
  364. };
  365. &gmac3 {
  366. status = "okay";
  367. phy-mode = "sgmii";
  368. qcom,id = <3>;
  369. phy-handle = <&phy7>;
  370. nvmem-cells = <&macaddr_fw_env_6>;
  371. nvmem-cell-names = "mac-address";
  372. };
  373. &adm_dma {
  374. status = "okay";
  375. };
  376. &hs_phy_1 {
  377. status = "okay";
  378. };
  379. &ss_phy_1 {
  380. status = "okay";
  381. };
  382. &usb3_1 {
  383. status = "okay";
  384. };
  385. &pcie0 {
  386. status = "okay";
  387. reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
  388. pinctrl-0 = <&pcie0_pins>;
  389. pinctrl-names = "default";
  390. bridge@0,0 {
  391. reg = <0x00000000 0 0 0 0>;
  392. #address-cells = <3>;
  393. #size-cells = <2>;
  394. ranges;
  395. wifi0: wifi@1,0 {
  396. compatible = "pci168c,0046";
  397. reg = <0x00010000 0 0 0 0>;
  398. nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
  399. nvmem-cell-names = "pre-calibration", "mac-address";
  400. };
  401. };
  402. };
  403. &pcie1 {
  404. status = "okay";
  405. reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
  406. pinctrl-0 = <&pcie1_pins>;
  407. pinctrl-names = "default";
  408. max-link-speed = <1>;
  409. bridge@0,0 {
  410. reg = <0x00000000 0 0 0 0>;
  411. #address-cells = <3>;
  412. #size-cells = <2>;
  413. ranges;
  414. wifi1: wifi@1,0 {
  415. compatible = "pci168c,0040";
  416. reg = <0x00010000 0 0 0 0>;
  417. nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
  418. nvmem-cell-names = "pre-calibration", "mac-address";
  419. };
  420. };
  421. };