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- From 4bbe44513bf9dc7041b2ce4aac6e841a0e10d2e6 Mon Sep 17 00:00:00 2001
- From: Weijie Gao <[email protected]>
- Date: Wed, 31 Aug 2022 19:04:29 +0800
- Subject: [PATCH 09/32] net: mediatek: add support for MediaTek MT7981/MT7986
- This patch adds support for MediaTek MT7981 and MT7986. Both chips uses
- PDMA v2.
- Reviewed-by: Ramon Fried <[email protected]>
- Signed-off-by: Weijie Gao <[email protected]>
- ---
- drivers/net/mtk_eth.c | 27 +++++++++++++++++++++++++++
- drivers/net/mtk_eth.h | 5 +++++
- 2 files changed, 32 insertions(+)
- --- a/drivers/net/mtk_eth.c
- +++ b/drivers/net/mtk_eth.c
- @@ -115,6 +115,7 @@ struct mtk_eth_priv {
- int force_mode;
- int speed;
- int duplex;
- + bool pn_swap;
-
- struct phy_device *phydev;
- int phy_interface;
- @@ -1057,6 +1058,12 @@ static void mtk_sgmii_init(struct mtk_et
- /* SGMII force mode setting */
- writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE);
-
- + /* SGMII PN SWAP setting */
- + if (priv->pn_swap) {
- + setbits_le32(priv->sgmii_base + SGMSYS_QPHY_WRAP_CTRL,
- + SGMII_PN_SWAP_TX_RX);
- + }
- +
- /* Release PHYA power down state */
- clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL,
- SGMII_PHYA_PWD, 0);
- @@ -1470,6 +1477,8 @@ static int mtk_eth_of_to_plat(struct ude
- dev_err(dev, "Unable to find sgmii\n");
- return -ENODEV;
- }
- +
- + priv->pn_swap = ofnode_read_bool(args.node, "pn_swap");
- }
-
- /* check for switch first, otherwise phy will be used */
- @@ -1520,6 +1529,22 @@ static int mtk_eth_of_to_plat(struct ude
- return 0;
- }
-
- +static const struct mtk_soc_data mt7986_data = {
- + .caps = MT7986_CAPS,
- + .ana_rgc3 = 0x128,
- + .pdma_base = PDMA_V2_BASE,
- + .txd_size = sizeof(struct mtk_tx_dma_v2),
- + .rxd_size = sizeof(struct mtk_rx_dma_v2),
- +};
- +
- +static const struct mtk_soc_data mt7981_data = {
- + .caps = MT7986_CAPS,
- + .ana_rgc3 = 0x128,
- + .pdma_base = PDMA_V2_BASE,
- + .txd_size = sizeof(struct mtk_tx_dma_v2),
- + .rxd_size = sizeof(struct mtk_rx_dma_v2),
- +};
- +
- static const struct mtk_soc_data mt7629_data = {
- .ana_rgc3 = 0x128,
- .pdma_base = PDMA_V1_BASE,
- @@ -1549,6 +1574,8 @@ static const struct mtk_soc_data mt7621_
- };
-
- static const struct udevice_id mtk_eth_ids[] = {
- + { .compatible = "mediatek,mt7986-eth", .data = (ulong)&mt7986_data },
- + { .compatible = "mediatek,mt7981-eth", .data = (ulong)&mt7981_data },
- { .compatible = "mediatek,mt7629-eth", .data = (ulong)&mt7629_data },
- { .compatible = "mediatek,mt7623-eth", .data = (ulong)&mt7623_data },
- { .compatible = "mediatek,mt7622-eth", .data = (ulong)&mt7622_data },
- --- a/drivers/net/mtk_eth.h
- +++ b/drivers/net/mtk_eth.h
- @@ -36,6 +36,8 @@ enum mkt_eth_capabilities {
-
- #define MT7623_CAPS (MTK_GMAC1_TRGMII)
-
- +#define MT7986_CAPS (MTK_NETSYS_V2)
- +
- /* Frame Engine Register Bases */
- #define PDMA_V1_BASE 0x0800
- #define PDMA_V2_BASE 0x6000
- @@ -72,6 +74,9 @@ enum mkt_eth_capabilities {
- #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
- #define SGMII_PHYA_PWD BIT(4)
-
- +#define SGMSYS_QPHY_WRAP_CTRL 0xec
- +#define SGMII_PN_SWAP_TX_RX 0x03
- +
- #define SGMSYS_GEN2_SPEED 0x2028
- #define SGMSYS_GEN2_SPEED_V2 0x128
- #define SGMSYS_SPEED_2500 BIT(2)
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