mt7622-totolink-a8000ru.dts 6.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/leds/common.h>
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include "mt7622.dtsi"
  7. #include "mt6380.dtsi"
  8. / {
  9. model = "TOTOLINK A8000RU";
  10. compatible = "totolink,a8000ru", "mediatek,mt7622";
  11. aliases {
  12. label-mac-device = &gmac0;
  13. led-boot = &led_status;
  14. led-failsafe = &led_status;
  15. led-running = &led_status;
  16. led-upgrade = &led_status;
  17. serial0 = &uart0;
  18. };
  19. chosen {
  20. stdout-path = "serial0:115200n8";
  21. bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  22. };
  23. cpus {
  24. cpu@0 {
  25. proc-supply = <&mt6380_vcpu_reg>;
  26. sram-supply = <&mt6380_vm_reg>;
  27. };
  28. cpu@1 {
  29. proc-supply = <&mt6380_vcpu_reg>;
  30. sram-supply = <&mt6380_vm_reg>;
  31. };
  32. };
  33. gpio-keys {
  34. compatible = "gpio-keys";
  35. reset {
  36. label = "reset";
  37. linux,code = <KEY_RESTART>;
  38. gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  39. };
  40. wps {
  41. label = "wps";
  42. linux,code = <KEY_WPS_BUTTON>;
  43. gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  44. };
  45. };
  46. gpio-leds {
  47. compatible = "gpio-leds";
  48. led_status: status_red {
  49. function = LED_FUNCTION_STATUS;
  50. color = <LED_COLOR_ID_RED>;
  51. gpios = <&pio 81 GPIO_ACTIVE_LOW>;
  52. default-state = "on";
  53. };
  54. };
  55. reg_1p8v: regulator-1p8v {
  56. compatible = "regulator-fixed";
  57. regulator-name = "fixed-1.8V";
  58. regulator-min-microvolt = <1800000>;
  59. regulator-max-microvolt = <1800000>;
  60. regulator-always-on;
  61. };
  62. reg_3p3v: regulator-3p3v {
  63. compatible = "regulator-fixed";
  64. regulator-name = "fixed-3.3V";
  65. regulator-min-microvolt = <3300000>;
  66. regulator-max-microvolt = <3300000>;
  67. regulator-boot-on;
  68. regulator-always-on;
  69. };
  70. reg_5v: regulator-5v {
  71. compatible = "regulator-fixed";
  72. regulator-name = "fixed-5V";
  73. regulator-min-microvolt = <5000000>;
  74. regulator-max-microvolt = <5000000>;
  75. regulator-boot-on;
  76. regulator-always-on;
  77. };
  78. rtkgsw: rtkgsw@0 {
  79. compatible = "mediatek,rtk-gsw";
  80. mediatek,ethsys = <&ethsys>;
  81. mediatek,mdio = <&mdio>;
  82. mediatek,reset-pin = <&pio 54 0>;
  83. status = "okay";
  84. };
  85. };
  86. &pcie0 {
  87. pinctrl-names = "default";
  88. pinctrl-0 = <&pcie0_pins>;
  89. status = "okay";
  90. };
  91. &slot0 {
  92. mt7615@0,0 {
  93. reg = <0x0000 0 0 0 0>;
  94. mediatek,mtd-eeprom = <&factory 0x5000>;
  95. ieee80211-freq-limit = <5490000 6000000>;
  96. };
  97. };
  98. &pcie1 {
  99. pinctrl-names = "default";
  100. pinctrl-0 = <&pcie1_pins>;
  101. status = "okay";
  102. };
  103. &slot1 {
  104. mt7615@0,0 {
  105. reg = <0x0000 0 0 0 0>;
  106. mediatek,mtd-eeprom = <&factory 0x10000>;
  107. ieee80211-freq-limit = <5000000 5490000>;
  108. };
  109. };
  110. &pio {
  111. eth_pins: eth-pins {
  112. mux {
  113. function = "eth";
  114. groups = "mdc_mdio", "rgmii_via_gmac2";
  115. };
  116. };
  117. pcie0_pins: pcie0-pins {
  118. mux {
  119. function = "pcie";
  120. groups = "pcie0_pad_perst",
  121. "pcie0_1_waken",
  122. "pcie0_1_clkreq";
  123. };
  124. };
  125. pcie1_pins: pcie1-pins {
  126. mux {
  127. function = "pcie";
  128. groups = "pcie1_pad_perst",
  129. "pcie1_0_waken",
  130. "pcie1_0_clkreq";
  131. };
  132. };
  133. pmic_bus_pins: pmic-bus-pins {
  134. mux {
  135. function = "pmic";
  136. groups = "pmic_bus";
  137. };
  138. };
  139. /* serial NAND is shared pin with SPI-NOR */
  140. serial_nand_pins: serial-nand-pins {
  141. mux {
  142. function = "flash";
  143. groups = "snfi";
  144. };
  145. };
  146. uart0_pins: uart0-pins {
  147. mux {
  148. function = "uart";
  149. groups = "uart0_0_tx_rx" ;
  150. };
  151. };
  152. watchdog_pins: watchdog-pins {
  153. mux {
  154. function = "watchdog";
  155. groups = "watchdog";
  156. };
  157. };
  158. epa_elna_pins: epa-elna-pins {
  159. mux {
  160. function = "antsel";
  161. groups = "antsel0", "antsel1", "antsel2", "antsel3",
  162. "antsel4", "antsel5", "antsel6", "antsel7",
  163. "antsel8", "antsel9", "antsel12", "antsel13",
  164. "antsel14", "antsel15", "antsel16", "antsel17";
  165. };
  166. };
  167. };
  168. &eth {
  169. status = "okay";
  170. pinctrl-names = "default";
  171. pinctrl-0 = <&eth_pins>;
  172. gmac0: mac@0 {
  173. compatible = "mediatek,eth-mac";
  174. reg = <0>;
  175. nvmem-cells = <&macaddr_factory_2a>;
  176. nvmem-cell-names = "mac-address";
  177. phy-connection-type = "2500base-x";
  178. fixed-link {
  179. speed = <2500>;
  180. full-duplex;
  181. pause;
  182. };
  183. };
  184. gmac1: mac@1 {
  185. compatible = "mediatek,eth-mac";
  186. reg = <1>;
  187. phy-mode = "rgmii";
  188. nvmem-cells = <&macaddr_factory_24>;
  189. nvmem-cell-names = "mac-address";
  190. fixed-link {
  191. speed = <1000>;
  192. full-duplex;
  193. pause;
  194. };
  195. };
  196. mdio: mdio-bus {
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. };
  200. };
  201. &pwrap {
  202. pinctrl-names = "default";
  203. pinctrl-0 = <&pmic_bus_pins>;
  204. status = "okay";
  205. };
  206. &bch {
  207. status = "okay";
  208. };
  209. &snfi {
  210. pinctrl-names = "default";
  211. pinctrl-0 = <&serial_nand_pins>;
  212. status = "okay";
  213. flash@0 {
  214. compatible = "spi-nand";
  215. reg = <0>;
  216. spi-tx-bus-width = <4>;
  217. spi-rx-bus-width = <4>;
  218. nand-ecc-engine = <&snfi>;
  219. mediatek,bmt-v2;
  220. partitions {
  221. compatible = "fixed-partitions";
  222. #address-cells = <1>;
  223. #size-cells = <1>;
  224. partition@0 {
  225. label = "Preloader";
  226. reg = <0x0 0x80000>;
  227. read-only;
  228. };
  229. partition@80000 {
  230. label = "ATF";
  231. reg = <0x80000 0x40000>;
  232. read-only;
  233. };
  234. partition@c0000 {
  235. label = "u-boot";
  236. reg = <0xc0000 0x80000>;
  237. read-only;
  238. };
  239. partition@140000 {
  240. label = "u-boot-env";
  241. reg = <0x140000 0x80000>;
  242. read-only;
  243. };
  244. factory: partition@1c0000 {
  245. label = "factory";
  246. reg = <0x1c0000 0x40000>;
  247. read-only;
  248. nvmem-layout {
  249. compatible = "fixed-layout";
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. macaddr_factory_24: macaddr@24 {
  253. reg = <0x24 0x6>;
  254. };
  255. macaddr_factory_2a: macaddr@2a {
  256. reg = <0x2a 0x6>;
  257. };
  258. };
  259. };
  260. partition@200000 {
  261. label = "ubi";
  262. reg = <0x200000 0x6400000>;
  263. };
  264. partition@6600000 {
  265. label = "User_data";
  266. reg = <0x6600000 0x100000>;
  267. };
  268. /* size of this partition varies due to BMT & bad blocks. */
  269. partition@6700000 {
  270. label = "reserved";
  271. reg = <0x6700000 0>;
  272. };
  273. };
  274. };
  275. };
  276. &ssusb {
  277. vusb33-supply = <&reg_3p3v>;
  278. vbus-supply = <&reg_5v>;
  279. status = "okay";
  280. };
  281. &u3phy {
  282. status = "okay";
  283. };
  284. &uart0 {
  285. pinctrl-names = "default";
  286. pinctrl-0 = <&uart0_pins>;
  287. status = "okay";
  288. };
  289. &watchdog {
  290. pinctrl-names = "default";
  291. pinctrl-0 = <&watchdog_pins>;
  292. status = "okay";
  293. };
  294. &wmac {
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&epa_elna_pins>;
  297. mediatek,mtd-eeprom = <&factory 0x0>;
  298. status = "okay";
  299. };