mt7981b-cetron-ct3003.dts 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7981.dtsi"
  7. / {
  8. model = "Cetron CT3003";
  9. compatible = "cetron,ct3003", "mediatek,mt7981";
  10. aliases {
  11. serial0 = &uart0;
  12. label-mac-device = &gmac0;
  13. led-boot = &led_status_red;
  14. led-failsafe = &led_status_red;
  15. led-running = &led_status_green;
  16. led-upgrade = &led_status_green;
  17. };
  18. chosen {
  19. stdout-path = "serial0:115200n8";
  20. };
  21. memory {
  22. reg = <0 0x40000000 0 0x10000000>;
  23. };
  24. gpio-keys {
  25. compatible = "gpio-keys";
  26. reset {
  27. label = "reset";
  28. linux,code = <KEY_RESTART>;
  29. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  30. };
  31. wps {
  32. label = "wps";
  33. linux,code = <KEY_WPS_BUTTON>;
  34. gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  35. };
  36. };
  37. leds {
  38. compatible = "gpio-leds";
  39. led_status_red: led_status_red {
  40. function = LED_FUNCTION_STATUS;
  41. color = <LED_COLOR_ID_RED>;
  42. gpios = <&pio 3 GPIO_ACTIVE_LOW>;
  43. };
  44. led_status_green: led_status_green {
  45. function = LED_FUNCTION_STATUS;
  46. color = <LED_COLOR_ID_GREEN>;
  47. gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  48. };
  49. };
  50. };
  51. &eth {
  52. status = "okay";
  53. gmac0: mac@0 {
  54. compatible = "mediatek,eth-mac";
  55. reg = <0>;
  56. phy-mode = "2500base-x";
  57. nvmem-cells = <&macaddr_art_0 0>;
  58. nvmem-cell-names = "mac-address";
  59. fixed-link {
  60. speed = <2500>;
  61. full-duplex;
  62. pause;
  63. };
  64. };
  65. };
  66. &mdio_bus {
  67. switch: switch@1f {
  68. compatible = "mediatek,mt7531";
  69. reg = <31>;
  70. reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  71. interrupt-controller;
  72. #interrupt-cells = <1>;
  73. interrupt-parent = <&pio>;
  74. interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  75. };
  76. };
  77. &spi0 {
  78. pinctrl-names = "default";
  79. pinctrl-0 = <&spi0_flash_pins>;
  80. status = "okay";
  81. spi_nand@0 {
  82. compatible = "spi-nand";
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. reg = <0>;
  86. spi-max-frequency = <52000000>;
  87. spi-tx-bus-width = <4>;
  88. spi-rx-bus-width = <4>;
  89. mediatek,nmbm;
  90. mediatek,bmt-max-ratio = <1>;
  91. mediatek,bmt-max-reserved-blocks = <64>;
  92. partitions {
  93. compatible = "fixed-partitions";
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. partition@0 {
  97. label = "BL2";
  98. reg = <0x0000000 0x0100000>;
  99. read-only;
  100. };
  101. partition@100000 {
  102. label = "u-boot-env";
  103. reg = <0x0100000 0x0080000>;
  104. };
  105. partition@180000 {
  106. label = "art";
  107. reg = <0x0180000 0x0100000>;
  108. read-only;
  109. nvmem-layout {
  110. compatible = "fixed-layout";
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. macaddr_art_0: macaddr@0 {
  114. compatible = "mac-base";
  115. reg = <0x0 0x6>;
  116. #nvmem-cell-cells = <1>;
  117. };
  118. };
  119. };
  120. factory: partition@280000 {
  121. label = "Factory";
  122. reg = <0x0280000 0x0100000>;
  123. read-only;
  124. };
  125. partition@380000 {
  126. label = "FIP";
  127. reg = <0x0380000 0x0200000>;
  128. read-only;
  129. };
  130. partition@580000 {
  131. label = "ubi";
  132. reg = <0x0580000 0x2000000>;
  133. };
  134. partition@2580000 {
  135. label = "ubi_backup";
  136. reg = <0x2580000 0x2000000>;
  137. };
  138. partition@4580000 {
  139. label = "Config_backup";
  140. reg = <0x4580000 0x0400000>;
  141. };
  142. };
  143. };
  144. };
  145. &switch {
  146. ports {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. port@0 {
  150. reg = <0>;
  151. label = "lan1";
  152. };
  153. port@1 {
  154. reg = <1>;
  155. label = "lan2";
  156. };
  157. port@2 {
  158. reg = <2>;
  159. label = "lan3";
  160. };
  161. port@3 {
  162. reg = <3>;
  163. label = "wan";
  164. nvmem-cells = <&macaddr_art_0 3>;
  165. nvmem-cell-names = "mac-address";
  166. };
  167. port@6 {
  168. reg = <6>;
  169. ethernet = <&gmac0>;
  170. phy-mode = "2500base-x";
  171. fixed-link {
  172. speed = <2500>;
  173. full-duplex;
  174. pause;
  175. };
  176. };
  177. };
  178. };
  179. &pio {
  180. spi0_flash_pins: spi0-pins {
  181. mux {
  182. function = "spi";
  183. groups = "spi0", "spi0_wp_hold";
  184. };
  185. conf-pu {
  186. pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
  187. drive-strength = <MTK_DRIVE_8mA>;
  188. bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
  189. };
  190. conf-pd {
  191. pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
  192. drive-strength = <MTK_DRIVE_8mA>;
  193. bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
  194. };
  195. };
  196. };
  197. &uart0 {
  198. status = "okay";
  199. };
  200. &watchdog {
  201. status = "okay";
  202. };
  203. &wifi {
  204. status = "okay";
  205. mediatek,mtd-eeprom = <&factory 0x0>;
  206. };