mt7981b-yuncore-ax835.dts 4.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include "mt7981.dtsi"
  4. / {
  5. compatible = "yuncore,ax835", "mediatek,mt7981";
  6. model = "YunCore AX835";
  7. aliases {
  8. ethernet0 = &gmac0;
  9. led-boot = &led_system;
  10. led-failsafe = &led_system;
  11. led-running = &led_system;
  12. led-upgrade = &led_system;
  13. serial0 = &uart0;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. gpio-keys {
  19. compatible = "gpio-keys";
  20. reset {
  21. label = "reset";
  22. linux,code = <KEY_RESTART>;
  23. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  24. };
  25. };
  26. reg_led_vbus {
  27. compatible = "regulator-fixed";
  28. regulator-name = "led_vbus";
  29. regulator-min-microvolt = <3300000>;
  30. regulator-max-microvolt = <3300000>;
  31. regulator-always-on;
  32. gpio = <&pio 5 GPIO_ACTIVE_HIGH>;
  33. };
  34. leds {
  35. compatible = "gpio-leds";
  36. led_system: led_system {
  37. label = "red:system";
  38. gpios = <&pio 4 GPIO_ACTIVE_LOW>;
  39. };
  40. led_wifi24 {
  41. label = "green:wifi2";
  42. gpios = <&pio 34 GPIO_ACTIVE_LOW>;
  43. linux,default-trigger = "phy0tpt";
  44. };
  45. led_wifi5 {
  46. label = "blue:wifi5";
  47. gpios = <&pio 35 GPIO_ACTIVE_LOW>;
  48. linux,default-trigger = "phy1tpt";
  49. };
  50. led_hwwatchdog {
  51. // a gpio-wdt watchdog couldn't be made to work.
  52. // the device rebooted after 5 minutes.
  53. label = "hwwatchdog";
  54. gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  55. linux,default-trigger = "timer";
  56. led-pattern = <1000>, <1000>;
  57. };
  58. // there's another "syswatchdog" on gpio2
  59. };
  60. };
  61. &eth {
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&mdio_pins>;
  64. status = "okay";
  65. gmac0: mac@0 {
  66. compatible = "mediatek,eth-mac";
  67. reg = <0>;
  68. phy-mode = "2500base-x";
  69. nvmem-cell-names = "mac-address";
  70. nvmem-cells = <&macaddr_factory_2a>;
  71. fixed-link {
  72. speed = <2500>;
  73. full-duplex;
  74. pause;
  75. };
  76. };
  77. };
  78. &mdio_bus {
  79. switch: switch@1f {
  80. compatible = "mediatek,mt7531";
  81. reg = <31>;
  82. reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  83. };
  84. };
  85. &pio {
  86. spi0_flash_pins: spi0-pins {
  87. mux {
  88. function = "spi";
  89. groups = "spi0", "spi0_wp_hold";
  90. };
  91. };
  92. spi2_flash_pins: spi2-pins {
  93. mux {
  94. function = "spi";
  95. groups = "spi2", "spi2_wp_hold";
  96. };
  97. conf-pu {
  98. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  99. drive-strength = <8>;
  100. bias-pull-up = <103>;
  101. };
  102. conf-pd {
  103. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  104. drive-strength = <8>;
  105. bias-pull-down = <103>;
  106. };
  107. };
  108. };
  109. &spi0 {
  110. pinctrl-names = "default";
  111. pinctrl-0 = <&spi0_flash_pins>;
  112. status = "disabled";
  113. };
  114. &spi2 {
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&spi2_flash_pins>;
  117. status = "okay";
  118. flash@0 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. compatible = "jedec,spi-nor";
  122. reg = <0>;
  123. spi-max-frequency = <52000000>;
  124. spi-tx-bus-width = <4>;
  125. spi-rx-bus-width = <4>;
  126. partitions {
  127. compatible = "fixed-partitions";
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. partition@00000 {
  131. label = "BL2";
  132. reg = <0x00000 0x40000>;
  133. read-only;
  134. };
  135. partition@40000 {
  136. label = "u-boot-env";
  137. reg = <0x40000 0x10000>;
  138. read-only;
  139. };
  140. factory: partition@50000 {
  141. label = "Factory";
  142. reg = <0x50000 0x10000>;
  143. read-only;
  144. nvmem-layout {
  145. compatible = "fixed-layout";
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. eeprom_factory: eeprom@0 {
  149. reg = <0x0 0x1000>;
  150. };
  151. macaddr_factory_4: macaddr@4 {
  152. reg = <0x4 0x6>;
  153. };
  154. macaddr_factory_24: macaddr@24 {
  155. reg = <0x24 0x6>;
  156. };
  157. macaddr_factory_2a: macaddr@2a {
  158. reg = <0x2a 0x6>;
  159. };
  160. };
  161. };
  162. partition@100000 {
  163. label = "FIP";
  164. reg = <0x100000 0x80000>;
  165. read-only;
  166. };
  167. partition@180000 {
  168. compatible = "denx,fit";
  169. label = "firmware";
  170. reg = <0x180000 0xe00000>;
  171. };
  172. };
  173. };
  174. };
  175. &switch {
  176. ports {
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. port@3 {
  180. reg = <3>;
  181. label = "lan";
  182. };
  183. port@4 {
  184. reg = <4>;
  185. label = "wan";
  186. };
  187. port@6 {
  188. reg = <6>;
  189. label = "cpu";
  190. ethernet = <&gmac0>;
  191. phy-mode = "2500base-x";
  192. fixed-link {
  193. speed = <2500>;
  194. full-duplex;
  195. pause;
  196. };
  197. };
  198. };
  199. };
  200. &uart0 {
  201. status = "okay";
  202. };
  203. &watchdog {
  204. status = "okay";
  205. };
  206. &wifi {
  207. status = "okay";
  208. nvmem-cells = <&eeprom_factory 0>;
  209. nvmem-cell-names = "eeprom";
  210. };