mt7986a-netcore-n60.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7986a.dtsi"
  7. / {
  8. model = "Netcore N60";
  9. compatible = "netcore,n60", "mediatek,mt7986a";
  10. aliases {
  11. serial0 = &uart0;
  12. label-mac-device = &gmac0;
  13. led-boot = &led_status_red;
  14. led-failsafe = &led_status_red;
  15. led-running = &led_status_blue;
  16. led-upgrade = &led_status_blue;
  17. };
  18. chosen {
  19. stdout-path = "serial0:115200n8";
  20. };
  21. memory {
  22. reg = <0 0x40000000 0 0x10000000>;
  23. };
  24. keys {
  25. compatible = "gpio-keys";
  26. reset {
  27. label = "reset";
  28. linux,code = <KEY_RESTART>;
  29. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  30. };
  31. mesh {
  32. label = "mesh";
  33. linux,code = <KEY_WPS_BUTTON>;
  34. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  35. };
  36. };
  37. leds {
  38. compatible = "gpio-leds";
  39. led_status_red: status-red {
  40. color = <LED_COLOR_ID_RED>;
  41. function = LED_FUNCTION_STATUS;
  42. gpios = <&pio 29 GPIO_ACTIVE_LOW>;
  43. };
  44. led_status_blue: status-blue {
  45. color = <LED_COLOR_ID_BLUE>;
  46. function = LED_FUNCTION_STATUS;
  47. gpios = <&pio 32 GPIO_ACTIVE_LOW>;
  48. };
  49. };
  50. };
  51. &crypto {
  52. status = "okay";
  53. };
  54. &eth {
  55. status = "okay";
  56. gmac0: mac@0 {
  57. compatible = "mediatek,eth-mac";
  58. reg = <0>;
  59. phy-mode = "2500base-x";
  60. nvmem-cells = <&macaddr_lan>;
  61. nvmem-cell-names = "mac-address";
  62. fixed-link {
  63. speed = <2500>;
  64. full-duplex;
  65. pause;
  66. };
  67. };
  68. gmac1: mac@1 {
  69. compatible = "mediatek,eth-mac";
  70. reg = <1>;
  71. phy-handle = <&phy6>;
  72. phy-mode = "2500base-x";
  73. nvmem-cells = <&macaddr_wan>;
  74. nvmem-cell-names = "mac-address";
  75. };
  76. mdio: mdio-bus {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. };
  80. };
  81. &mdio {
  82. reset-delay-us = <600>;
  83. reset-post-delay-us = <20000>;
  84. reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  85. phy6: phy@6 {
  86. compatible = "ethernet-phy-ieee802.3-c45";
  87. reg = <6>;
  88. mxl,led-config = <0x0 0x0 0x0 0x3f0>;
  89. };
  90. switch: switch@1f {
  91. compatible = "mediatek,mt7531";
  92. reg = <31>;
  93. reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  94. interrupt-controller;
  95. #interrupt-cells = <1>;
  96. interrupt-parent = <&pio>;
  97. interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  98. };
  99. };
  100. &switch {
  101. ports {
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. port@0 {
  105. reg = <0>;
  106. label = "lan1";
  107. };
  108. port@1 {
  109. reg = <1>;
  110. label = "lan2";
  111. };
  112. port@3 {
  113. reg = <3>;
  114. label = "lan3";
  115. };
  116. port@4 {
  117. reg = <4>;
  118. label = "lan4";
  119. };
  120. port@6 {
  121. reg = <6>;
  122. ethernet = <&gmac0>;
  123. phy-mode = "2500base-x";
  124. fixed-link {
  125. speed = <2500>;
  126. full-duplex;
  127. pause;
  128. };
  129. };
  130. };
  131. };
  132. &spi0 {
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&spi_flash_pins>;
  135. status = "okay";
  136. flash@0 {
  137. compatible = "spi-nand";
  138. #address-cells = <1>;
  139. #size-cells = <1>;
  140. reg = <0>;
  141. spi-max-frequency = <20000000>;
  142. spi-tx-bus-width = <4>;
  143. spi-rx-bus-width = <4>;
  144. partitions {
  145. compatible = "fixed-partitions";
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. partition@0 {
  149. label = "BL2";
  150. reg = <0x0000000 0x0100000>;
  151. read-only;
  152. };
  153. partition@100000 {
  154. label = "u-boot-env";
  155. reg = <0x0100000 0x0080000>;
  156. };
  157. factory: partition@180000 {
  158. label = "Factory";
  159. reg = <0x0180000 0x0200000>;
  160. read-only;
  161. };
  162. partition@380000 {
  163. label = "FIP";
  164. reg = <0x0380000 0x0200000>;
  165. read-only;
  166. };
  167. partition@580000 {
  168. label = "ubi";
  169. reg = <0x0580000 0x7280000>;
  170. };
  171. };
  172. };
  173. };
  174. &pio {
  175. spi_flash_pins: spi-flash-pins-33-to-38 {
  176. mux {
  177. function = "spi";
  178. groups = "spi0", "spi0_wp_hold";
  179. };
  180. conf-pu {
  181. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  182. drive-strength = <8>;
  183. mediatek,pull-up-adv = <0>; /* bias-disable */
  184. };
  185. conf-pd {
  186. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  187. drive-strength = <8>;
  188. mediatek,pull-down-adv = <0>; /* bias-disable */
  189. };
  190. };
  191. wf_2g_5g_pins: wf_2g_5g-pins {
  192. mux {
  193. function = "wifi";
  194. groups = "wf_2g", "wf_5g";
  195. };
  196. conf {
  197. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  198. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  199. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  200. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  201. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  202. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  203. "WF1_TOP_CLK", "WF1_TOP_DATA";
  204. drive-strength = <4>;
  205. };
  206. };
  207. };
  208. &trng {
  209. status = "okay";
  210. };
  211. &uart0 {
  212. status = "okay";
  213. };
  214. &watchdog {
  215. status = "okay";
  216. };
  217. &wifi {
  218. status = "okay";
  219. pinctrl-names = "default";
  220. pinctrl-0 = <&wf_2g_5g_pins>;
  221. mediatek,mtd-eeprom = <&factory 0x0>;
  222. };
  223. &factory {
  224. nvmem-layout {
  225. compatible = "fixed-layout";
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. macaddr_lan: macaddr@1fef20 {
  229. reg = <0x1fef20 0x6>;
  230. };
  231. macaddr_wan: macaddr@1fef26 {
  232. reg = <0x1fef26 0x6>;
  233. };
  234. };
  235. };