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- From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
- From: Kathiravan Thirumoorthy <[email protected]>
- Date: Thu, 14 Sep 2023 12:29:57 +0530
- Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
- provider
- While the kernel is booting up, APSS PLL will be running at 800MHz with
- GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
- configured and select the rate based on the opp table and the source will
- be changed to APSS_PLL_EARLY.
- Without this patch, CPU Freq driver reports that CPU is running at 24MHz
- instead of the 800MHz.
- Reviewed-by: Konrad Dybcio <[email protected]>
- Tested-by: Robert Marko <[email protected]>
- Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
- ---
- drivers/clk/qcom/apss-ipq6018.c | 3 +++
- 1 file changed, 3 insertions(+)
- --- a/drivers/clk/qcom/apss-ipq6018.c
- +++ b/drivers/clk/qcom/apss-ipq6018.c
- @@ -20,16 +20,19 @@
-
- enum {
- P_XO,
- + P_GPLL0,
- P_APSS_PLL_EARLY,
- };
-
- static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
- { .fw_name = "xo" },
- + { .fw_name = "gpll0" },
- { .fw_name = "pll" },
- };
-
- static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
- { P_XO, 0 },
- + { P_GPLL0, 4 },
- { P_APSS_PLL_EARLY, 5 },
- };
-
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