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0053-v6.7-clk-qcom-gcc-ipq6018-add-QUP6-I2C-clock.patch 2.1 KB

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  1. From 3dcf7b59393812a5fbd83f8cd8d34b94afb4c4d1 Mon Sep 17 00:00:00 2001
  2. From: Robert Marko <[email protected]>
  3. Date: Sat, 21 Oct 2023 13:55:18 +0200
  4. Subject: [PATCH] clk: qcom: gcc-ipq6018: add QUP6 I2C clock
  5. QUP6 I2C clock is listed in the dt bindings but it was never included in
  6. the GCC driver.
  7. So lets add support for it, it is marked as criticial as it is used by RPM
  8. to communicate to the external PMIC over I2C so this clock must not be
  9. disabled.
  10. Signed-off-by: Robert Marko <[email protected]>
  11. Reviewed-by: Kathiravan Thirumoorthy <[email protected]>
  12. Reviewed-by: Konrad Dybcio <[email protected]>
  13. Link: https://lore.kernel.org/r/[email protected]
  14. Signed-off-by: Bjorn Andersson <[email protected]>
  15. ---
  16. drivers/clk/qcom/gcc-ipq6018.c | 21 +++++++++++++++++++++
  17. 1 file changed, 21 insertions(+)
  18. --- a/drivers/clk/qcom/gcc-ipq6018.c
  19. +++ b/drivers/clk/qcom/gcc-ipq6018.c
  20. @@ -2121,6 +2121,26 @@ static struct clk_branch gcc_blsp1_qup5_
  21. },
  22. };
  23. +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
  24. + .halt_reg = 0x07010,
  25. + .clkr = {
  26. + .enable_reg = 0x07010,
  27. + .enable_mask = BIT(0),
  28. + .hw.init = &(struct clk_init_data){
  29. + .name = "gcc_blsp1_qup6_i2c_apps_clk",
  30. + .parent_hws = (const struct clk_hw *[]){
  31. + &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
  32. + .num_parents = 1,
  33. + /*
  34. + * RPM uses QUP6 I2C to communicate with the external
  35. + * PMIC so it must not be disabled.
  36. + */
  37. + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
  38. + .ops = &clk_branch2_ops,
  39. + },
  40. + },
  41. +};
  42. +
  43. static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
  44. .halt_reg = 0x0700c,
  45. .clkr = {
  46. @@ -4277,6 +4297,7 @@ static struct clk_regmap *gcc_ipq6018_cl
  47. [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
  48. [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
  49. [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
  50. + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
  51. [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
  52. [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
  53. [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,