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- From 04d2fc6a551bbd972a6428059b45ce79cb9de9d7 Mon Sep 17 00:00:00 2001
- From: Robert Marko <[email protected]>
- Date: Fri, 6 May 2022 22:38:24 +0200
- Subject: [PATCH] arm64: dts: qcom: ipq8074: add QFPROM fuses
- Add the QFPROM node and CPR fuses.
- Signed-off-by: Robert Marko <[email protected]>
- ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 107 ++++++++++++++++++++++++++
- 1 file changed, 107 insertions(+)
- --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- @@ -349,6 +349,106 @@
- reg = <0x000a4000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- +
- + cpr_efuse_speedbin: speedbin@125 {
- + reg = <0x125 0x1>;
- + bits = <0 3>;
- + };
- +
- + cpr_efuse_boost_cfg: boost_cfg@125 {
- + reg = <0x125 0x1>;
- + bits = <3 3>;
- + };
- +
- + cpr_efuse_misc_volt_adj: misc_volt_adj@125 {
- + reg = <0x125 0x1>;
- + bits = <3 3>;
- + };
- +
- + cpr_efuse_boost_volt: boost_volt@126 {
- + reg = <0x126 0x1>;
- + bits = <6 1>;
- + };
- +
- + cpr_efuse_revision: revision@23e {
- + reg = <0x23e 0x1>;
- + bits = <5 3>;
- + };
- +
- + cpr_efuse_ro_sel0: rosel0@249 {
- + reg = <0x249 0x1>;
- + bits = <0 4>;
- + };
- +
- + cpr_efuse_ro_sel1: rosel1@248 {
- + reg = <0x248 0x1>;
- + bits = <4 4>;
- + };
- +
- + cpr_efuse_ro_sel2: rosel2@248 {
- + reg = <0x248 0x2>;
- + bits = <0 4>;
- + };
- +
- + cpr_efuse_ro_sel3: rosel3@249 {
- + reg = <0x249 0x1>;
- + bits = <4 4>;
- + };
- +
- + cpr_efuse_init_voltage0: ivoltage0@23a {
- + reg = <0x23a 0x1>;
- + bits = <2 6>;
- + };
- +
- + cpr_efuse_init_voltage1: ivoltage1@239 {
- + reg = <0x239 0x2>;
- + bits = <4 6>;
- + };
- +
- + cpr_efuse_init_voltage2: ivoltage2@238 {
- + reg = <0x238 0x2>;
- + bits = <6 6>;
- + };
- +
- + cpr_efuse_init_voltage3: ivoltage3@238 {
- + reg = <0x238 0x1>;
- + bits = <0 6>;
- + };
- +
- + cpr_efuse_quot0: quot0@244 {
- + reg = <0x244 0x2>;
- + bits = <0 12>;
- + };
- +
- + cpr_efuse_quot1: quot1@242 {
- + reg = <0x242 0x2>;
- + bits = <4 12>;
- + };
- +
- + cpr_efuse_quot2: quot2@241 {
- + reg = <0x241 0x2>;
- + bits = <0 12>;
- + };
- +
- + cpr_efuse_quot3: quot3@245 {
- + reg = <0x245 0x2>;
- + bits = <4 12>;
- + };
- +
- + cpr_efuse_quot0_offset: quot0_offset@23d {
- + reg = <0x23d 0x2>;
- + bits = <6 7>;
- + };
- +
- + cpr_efuse_quot1_offset: quot1_offset@23c {
- + reg = <0x23c 0x2>;
- + bits = <7 7>;
- + };
- +
- + cpr_efuse_quot2_offset: quot2_offset@23c {
- + reg = <0x23c 0x1>;
- + bits = <0 7>;
- + };
- };
-
- prng: rng@e3000 {
|
