0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. From 32f95a0bc03886b38a53569466d5bee4a6d66875 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Wed, 2 Mar 2016 07:18:52 +0100
  4. Subject: [PATCH 48/53] net-next: mediatek: document MediaTek SoC ethernet
  5. binding
  6. This adds the binding documentation for the MediaTek Ethernet
  7. controller.
  8. Signed-off-by: John Crispin <[email protected]>
  9. Acked-by: Rob Herring <[email protected]>
  10. Cc: [email protected]
  11. ---
  12. .../devicetree/bindings/net/mediatek-net.txt | 77 ++++++++++++++++++++
  13. 1 file changed, 77 insertions(+)
  14. create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
  15. diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
  16. new file mode 100644
  17. index 0000000..5ca7929
  18. --- /dev/null
  19. +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
  20. @@ -0,0 +1,77 @@
  21. +MediaTek Frame Engine Ethernet controller
  22. +=========================================
  23. +
  24. +The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
  25. +have dual GMAC each represented by a child node..
  26. +
  27. +* Ethernet controller node
  28. +
  29. +Required properties:
  30. +- compatible: Should be "mediatek,mt7623-eth"
  31. +- reg: Address and length of the register set for the device
  32. +- interrupts: Should contain the frame engines interrupt
  33. +- clocks: the clock used by the core
  34. +- clock-names: the names of the clock listed in the clocks property. These are
  35. + "ethif", "esw", "gp2", "gp1"
  36. +- power-domains: phandle to the power domain that the ethernet is part of
  37. +- resets: Should contain a phandle to the ethsys reset signal
  38. +- reset-names: Should contain the reset signal name "eth"
  39. +- mediatek,ethsys: phandle to the syscon node that handles the port setup
  40. +- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
  41. + and driver current
  42. +
  43. +Optional properties:
  44. +- interrupt-parent: Should be the phandle for the interrupt controller
  45. + that services interrupts for this device
  46. +
  47. +
  48. +* Ethernet MAC node
  49. +
  50. +Required properties:
  51. +- compatible: Should be "mediatek,eth-mac"
  52. +- reg: The number of the MAC
  53. +- phy-handle: see ethernet.txt file in the same directory.
  54. +
  55. +Example:
  56. +
  57. +eth: ethernet@1b100000 {
  58. + compatible = "mediatek,mt7623-eth";
  59. + reg = <0 0x1b100000 0 0x20000>;
  60. + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  61. + <&ethsys CLK_ETHSYS_ESW>,
  62. + <&ethsys CLK_ETHSYS_GP2>,
  63. + <&ethsys CLK_ETHSYS_GP1>;
  64. + clock-names = "ethif", "esw", "gp2", "gp1";
  65. + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
  66. + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  67. + resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  68. + reset-names = "eth";
  69. + mediatek,ethsys = <&ethsys>;
  70. + mediatek,pctl = <&syscfg_pctl_a>;
  71. + #address-cells = <1>;
  72. + #size-cells = <0>;
  73. +
  74. + gmac1: mac@0 {
  75. + compatible = "mediatek,eth-mac";
  76. + reg = <0>;
  77. + phy-handle = <&phy0>;
  78. + };
  79. +
  80. + gmac2: mac@1 {
  81. + compatible = "mediatek,eth-mac";
  82. + reg = <1>;
  83. + phy-handle = <&phy1>;
  84. + };
  85. +
  86. + mdio-bus {
  87. + phy0: ethernet-phy@0 {
  88. + reg = <0>;
  89. + phy-mode = "rgmii";
  90. + };
  91. +
  92. + phy1: ethernet-phy@1 {
  93. + reg = <1>;
  94. + phy-mode = "rgmii";
  95. + };
  96. + };
  97. +};
  98. --
  99. 1.7.10.4