733-v6.2-03-net-mediatek-sgmii-fix-duplex-configuration.patch 2.2 KB

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  1. From 9d32637122de88f1ef614c29703f0e050cad342e Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <[email protected]>
  3. Date: Wed, 1 Feb 2023 19:23:30 +0100
  4. Subject: [PATCH] net: mediatek: sgmii: fix duplex configuration
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8. The logic of the duplex bit is inverted. Setting it means half
  9. duplex, not full duplex.
  10. Fix and rename macro to avoid confusion.
  11. Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
  12. Reviewed-by: Russell King (Oracle) <[email protected]>
  13. Signed-off-by: Bjørn Mork <[email protected]>
  14. Acked-by: Daniel Golle <[email protected]>
  15. Tested-by: Daniel Golle <[email protected]>
  16. Signed-off-by: Jakub Kicinski <[email protected]>
  17. ---
  18. drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-
  19. drivers/net/ethernet/mediatek/mtk_sgmii.c | 6 +++---
  20. 2 files changed, 4 insertions(+), 4 deletions(-)
  21. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  22. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  23. @@ -523,7 +523,7 @@
  24. #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
  25. #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
  26. #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
  27. -#define SGMII_DUPLEX_FULL BIT(4)
  28. +#define SGMII_DUPLEX_HALF BIT(4)
  29. #define SGMII_IF_MODE_BIT5 BIT(5)
  30. #define SGMII_REMOTE_FAULT_DIS BIT(8)
  31. #define SGMII_CODE_SYNC_SET_VAL BIT(9)
  32. --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  33. +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  34. @@ -66,7 +66,7 @@ static int mtk_pcs_setup_mode_force(stru
  35. /* Set the speed etc but leave the duplex unchanged */
  36. regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  37. - val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
  38. + val &= SGMII_DUPLEX_HALF | ~SGMII_IF_MODE_MASK;
  39. val |= SGMII_SPEED_1000;
  40. regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  41. @@ -131,9 +131,10 @@ static void mtk_pcs_link_up(struct phyli
  42. /* SGMII force duplex setting */
  43. regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
  44. - val &= ~SGMII_DUPLEX_FULL;
  45. - if (duplex == DUPLEX_FULL)
  46. - val |= SGMII_DUPLEX_FULL;
  47. +
  48. + val &= ~SGMII_DUPLEX_HALF;
  49. + if (duplex != DUPLEX_FULL)
  50. + val |= SGMII_DUPLEX_HALF;
  51. regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  52. }