qcom-ipq4018-jalapeno.dtsi 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2018, Robert Marko <[email protected]>
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. aliases {
  9. ethernet1 = &swport5;
  10. };
  11. soc {
  12. rng@22000 {
  13. status = "okay";
  14. };
  15. mdio@90000 {
  16. status = "okay";
  17. pinctrl-0 = <&mdio_pins>;
  18. pinctrl-names = "default";
  19. };
  20. counter@4a1000 {
  21. compatible = "qcom,qca-gcnt";
  22. reg = <0x4a1000 0x4>;
  23. };
  24. tcsr@1949000 {
  25. compatible = "qcom,tcsr";
  26. reg = <0x1949000 0x100>;
  27. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  28. };
  29. tcsr@194b000 {
  30. status = "okay";
  31. compatible = "qcom,tcsr";
  32. reg = <0x194b000 0x100>;
  33. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  34. };
  35. ess_tcsr@1953000 {
  36. compatible = "qcom,tcsr";
  37. reg = <0x1953000 0x1000>;
  38. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  39. };
  40. tcsr@1957000 {
  41. compatible = "qcom,tcsr";
  42. reg = <0x1957000 0x100>;
  43. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  44. };
  45. crypto@8e3a000 {
  46. status = "okay";
  47. };
  48. watchdog@b017000 {
  49. status = "okay";
  50. };
  51. };
  52. };
  53. &tlmm {
  54. mdio_pins: mdio_pinmux {
  55. pinmux_1 {
  56. pins = "gpio53";
  57. function = "mdio";
  58. };
  59. pinmux_2 {
  60. pins = "gpio52";
  61. function = "mdc";
  62. };
  63. pinconf {
  64. pins = "gpio52", "gpio53";
  65. bias-pull-up;
  66. };
  67. };
  68. serial_pins: serial_pinmux {
  69. mux {
  70. pins = "gpio60", "gpio61";
  71. function = "blsp_uart0";
  72. bias-disable;
  73. };
  74. };
  75. spi_0_pins: spi_0_pinmux {
  76. pin {
  77. function = "blsp_spi0";
  78. pins = "gpio55", "gpio56", "gpio57";
  79. drive-strength = <2>;
  80. bias-disable;
  81. };
  82. pin_cs {
  83. function = "gpio";
  84. pins = "gpio54", "gpio59";
  85. drive-strength = <2>;
  86. bias-disable;
  87. output-high;
  88. };
  89. };
  90. };
  91. &blsp_dma {
  92. status = "okay";
  93. };
  94. &blsp1_spi1 {
  95. status = "okay";
  96. pinctrl-0 = <&spi_0_pins>;
  97. pinctrl-names = "default";
  98. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
  99. flash@0 {
  100. status = "okay";
  101. compatible = "jedec,spi-nor";
  102. reg = <0>;
  103. spi-max-frequency = <24000000>;
  104. partitions {
  105. compatible = "fixed-partitions";
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. partition@0 {
  109. label = "SBL1";
  110. reg = <0x00000000 0x00040000>;
  111. read-only;
  112. };
  113. partition@40000 {
  114. label = "MIBIB";
  115. reg = <0x00040000 0x00020000>;
  116. read-only;
  117. };
  118. partition@60000 {
  119. label = "QSEE";
  120. reg = <0x00060000 0x00060000>;
  121. read-only;
  122. };
  123. partition@c0000 {
  124. label = "CDT";
  125. reg = <0x000c0000 0x00010000>;
  126. read-only;
  127. };
  128. partition@d0000 {
  129. label = "DDRPARAMS";
  130. reg = <0x000d0000 0x00010000>;
  131. read-only;
  132. };
  133. partition@e0000 {
  134. label = "APPSBLENV"; /* uboot env*/
  135. reg = <0x000e0000 0x00010000>;
  136. read-only;
  137. };
  138. partition@f0000 {
  139. label = "APPSBL"; /* uboot */
  140. reg = <0x000f0000 0x00080000>;
  141. read-only;
  142. };
  143. partition@170000 {
  144. label = "ART";
  145. reg = <0x00170000 0x00010000>;
  146. read-only;
  147. nvmem-layout {
  148. compatible = "fixed-layout";
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. precal_art_1000: precal@1000 {
  152. reg = <0x1000 0x2f20>;
  153. };
  154. precal_art_5000: precal@5000 {
  155. reg = <0x5000 0x2f20>;
  156. };
  157. };
  158. };
  159. };
  160. };
  161. spi-nand@1 {
  162. status = "okay";
  163. compatible = "spi-nand";
  164. reg = <1>;
  165. spi-max-frequency = <24000000>;
  166. partitions {
  167. compatible = "fixed-partitions";
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. partition@0 {
  171. label = "ubi";
  172. reg = <0x00000000 0x08000000>;
  173. };
  174. };
  175. };
  176. };
  177. &blsp1_uart1 {
  178. status = "okay";
  179. pinctrl-0 = <&serial_pins>;
  180. pinctrl-names = "default";
  181. };
  182. &cryptobam {
  183. status = "okay";
  184. };
  185. &gmac {
  186. status = "okay";
  187. };
  188. &switch {
  189. status = "okay";
  190. };
  191. &swport4 {
  192. status = "okay";
  193. label = "lan";
  194. };
  195. &swport5 {
  196. status = "okay";
  197. };
  198. &wifi0 {
  199. status = "okay";
  200. nvmem-cell-names = "pre-calibration";
  201. nvmem-cells = <&precal_art_1000>;
  202. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  203. };
  204. &wifi1 {
  205. status = "okay";
  206. nvmem-cell-names = "pre-calibration";
  207. nvmem-cells = <&precal_art_5000>;
  208. qcom,ath10k-calibration-variant = "8devices-Jalapeno";
  209. };
  210. &usb3 {
  211. status = "okay";
  212. };
  213. &usb3_ss_phy {
  214. status = "okay";
  215. };
  216. &usb3_hs_phy {
  217. status = "okay";
  218. };
  219. &usb2 {
  220. status = "okay";
  221. };
  222. &usb2_hs_phy {
  223. status = "okay";
  224. };