qcom-ipq4019-habanero-dvk.dts 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2019, Robert Marko <[email protected]> */
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/leds/common.h>
  7. #include <dt-bindings/soc/qcom,tcsr.h>
  8. / {
  9. model = "8devices Habanero DVK";
  10. compatible = "8dev,habanero-dvk";
  11. aliases {
  12. led-boot = &led_status;
  13. led-failsafe = &led_status;
  14. led-running = &led_status;
  15. led-upgrade = &led_upgrade;
  16. ethernet1 = &swport5;
  17. };
  18. soc {
  19. rng@22000 {
  20. status = "okay";
  21. };
  22. mdio@90000 {
  23. status = "okay";
  24. pinctrl-0 = <&mdio_pins>;
  25. pinctrl-names = "default";
  26. };
  27. counter@4a1000 {
  28. compatible = "qcom,qca-gcnt";
  29. reg = <0x4a1000 0x4>;
  30. };
  31. tcsr@1949000 {
  32. compatible = "qcom,tcsr";
  33. reg = <0x1949000 0x100>;
  34. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  35. };
  36. tcsr@194b000 {
  37. status = "okay";
  38. compatible = "qcom,tcsr";
  39. reg = <0x194b000 0x100>;
  40. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  41. };
  42. ess_tcsr@1953000 {
  43. compatible = "qcom,tcsr";
  44. reg = <0x1953000 0x1000>;
  45. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  46. };
  47. tcsr@1957000 {
  48. compatible = "qcom,tcsr";
  49. reg = <0x1957000 0x100>;
  50. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  51. };
  52. crypto@8e3a000 {
  53. status = "okay";
  54. };
  55. watchdog@b017000 {
  56. status = "okay";
  57. };
  58. };
  59. keys {
  60. compatible = "gpio-keys";
  61. reset {
  62. label = "reset";
  63. gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
  64. linux,code = <KEY_RESTART>;
  65. };
  66. };
  67. leds {
  68. compatible = "gpio-leds";
  69. led_status: status {
  70. function = LED_FUNCTION_STATUS;
  71. color = <LED_COLOR_ID_GREEN>;
  72. gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
  73. panic-indicator;
  74. };
  75. led_upgrade: upgrade {
  76. label = "green:upgrade";
  77. gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  78. };
  79. wlan2g {
  80. label = "green:wlan2g";
  81. gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
  82. linux,default-trigger = "phy0tpt";
  83. };
  84. wlan5g {
  85. label = "green:wlan5g";
  86. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  87. linux,default-trigger = "phy1tpt";
  88. };
  89. };
  90. };
  91. &vqmmc {
  92. status = "okay";
  93. };
  94. &sdhci {
  95. status = "okay";
  96. pinctrl-0 = <&sd_pins>;
  97. pinctrl-names = "default";
  98. cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
  99. vqmmc-supply = <&vqmmc>;
  100. };
  101. &qpic_bam {
  102. status = "okay";
  103. };
  104. &tlmm {
  105. mdio_pins: mdio_pinmux {
  106. mux_1 {
  107. pins = "gpio6";
  108. function = "mdio";
  109. bias-pull-up;
  110. };
  111. mux_2 {
  112. pins = "gpio7";
  113. function = "mdc";
  114. bias-pull-up;
  115. };
  116. };
  117. serial_pins: serial_pinmux {
  118. mux {
  119. pins = "gpio16", "gpio17";
  120. function = "blsp_uart0";
  121. bias-disable;
  122. };
  123. };
  124. spi_0_pins: spi_0_pinmux {
  125. pinmux {
  126. function = "blsp_spi0";
  127. pins = "gpio13", "gpio14", "gpio15";
  128. drive-strength = <12>;
  129. bias-disable;
  130. };
  131. pinmux_cs {
  132. function = "gpio";
  133. pins = "gpio12";
  134. drive-strength = <2>;
  135. bias-disable;
  136. output-high;
  137. };
  138. };
  139. nand_pins: nand_pins {
  140. pullups {
  141. pins = "gpio52", "gpio53", "gpio58", "gpio59";
  142. function = "qpic";
  143. bias-pull-up;
  144. };
  145. pulldowns {
  146. pins = "gpio54", "gpio55", "gpio56", "gpio57",
  147. "gpio60", "gpio62", "gpio63", "gpio64",
  148. "gpio65", "gpio66", "gpio67", "gpio68",
  149. "gpio69";
  150. function = "qpic";
  151. bias-pull-down;
  152. };
  153. };
  154. sd_pins: sd_pins {
  155. pinmux {
  156. function = "sdio";
  157. pins = "gpio23", "gpio24", "gpio25", "gpio26",
  158. "gpio28", "gpio29", "gpio30", "gpio31";
  159. drive-strength = <10>;
  160. };
  161. pinmux_sd_clk {
  162. function = "sdio";
  163. pins = "gpio27";
  164. drive-strength = <16>;
  165. };
  166. pinmux_sd7 {
  167. function = "sdio";
  168. pins = "gpio32";
  169. drive-strength = <10>;
  170. bias-disable;
  171. };
  172. };
  173. };
  174. &blsp_dma {
  175. status = "okay";
  176. };
  177. &blsp1_spi1 {
  178. status = "okay";
  179. pinctrl-0 = <&spi_0_pins>;
  180. pinctrl-names = "default";
  181. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  182. flash@0 {
  183. compatible = "jedec,spi-nor";
  184. spi-max-frequency = <24000000>;
  185. reg = <0>;
  186. partitions {
  187. compatible = "fixed-partitions";
  188. #address-cells = <1>;
  189. #size-cells = <1>;
  190. partition@0 {
  191. label = "SBL1";
  192. reg = <0x00000000 0x00040000>;
  193. read-only;
  194. };
  195. partition@40000 {
  196. label = "MIBIB";
  197. reg = <0x00040000 0x00020000>;
  198. read-only;
  199. };
  200. partition@60000 {
  201. label = "QSEE";
  202. reg = <0x00060000 0x00060000>;
  203. read-only;
  204. };
  205. partition@c0000 {
  206. label = "CDT";
  207. reg = <0x000c0000 0x00010000>;
  208. read-only;
  209. };
  210. partition@d0000 {
  211. label = "DDRPARAMS";
  212. reg = <0x000d0000 0x00010000>;
  213. read-only;
  214. };
  215. partition@e0000 {
  216. label = "APPSBLENV"; /* uboot env */
  217. reg = <0x000e0000 0x00010000>;
  218. read-only;
  219. };
  220. partition@f0000 {
  221. label = "APPSBL"; /* uboot */
  222. reg = <0x000f0000 0x00080000>;
  223. read-only;
  224. };
  225. partition@170000 {
  226. label = "ART";
  227. reg = <0x00170000 0x00010000>;
  228. read-only;
  229. nvmem-layout {
  230. compatible = "fixed-layout";
  231. #address-cells = <1>;
  232. #size-cells = <1>;
  233. precal_art_1000: precal@1000 {
  234. reg = <0x1000 0x2f20>;
  235. };
  236. precal_art_5000: precal@5000 {
  237. reg = <0x5000 0x2f20>;
  238. };
  239. };
  240. };
  241. partition@180000 {
  242. label = "cfg";
  243. reg = <0x00180000 0x00040000>;
  244. };
  245. partition@1c0000 {
  246. label = "firmware";
  247. compatible = "denx,fit";
  248. reg = <0x001c0000 0x01e40000>;
  249. };
  250. };
  251. };
  252. };
  253. /* Some DVK boards ship without NAND */
  254. &nand {
  255. status = "okay";
  256. pinctrl-0 = <&nand_pins>;
  257. pinctrl-names = "default";
  258. };
  259. &blsp1_uart1 {
  260. status = "okay";
  261. pinctrl-0 = <&serial_pins>;
  262. pinctrl-names = "default";
  263. };
  264. &cryptobam {
  265. status = "okay";
  266. };
  267. &pcie0 {
  268. status = "okay";
  269. perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
  270. wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
  271. /* Free slot for use */
  272. bridge@0,0 {
  273. reg = <0x00000000 0 0 0 0>;
  274. #address-cells = <3>;
  275. #size-cells = <2>;
  276. ranges;
  277. };
  278. };
  279. &gmac {
  280. status = "okay";
  281. };
  282. &switch {
  283. status = "okay";
  284. };
  285. &swport1 {
  286. status = "okay";
  287. };
  288. &swport2 {
  289. status = "okay";
  290. };
  291. &swport3 {
  292. status = "okay";
  293. };
  294. &swport4 {
  295. status = "okay";
  296. };
  297. &swport5 {
  298. status = "okay";
  299. };
  300. &wifi0 {
  301. status = "okay";
  302. nvmem-cell-names = "pre-calibration";
  303. nvmem-cells = <&precal_art_1000>;
  304. qcom,ath10k-calibration-variant = "8devices-Habanero";
  305. };
  306. &wifi1 {
  307. status = "okay";
  308. nvmem-cell-names = "pre-calibration";
  309. nvmem-cells = <&precal_art_5000>;
  310. qcom,ath10k-calibration-variant = "8devices-Habanero";
  311. };
  312. &usb3 {
  313. status = "okay";
  314. };
  315. &usb3_ss_phy {
  316. status = "okay";
  317. };
  318. &usb3_hs_phy {
  319. status = "okay";
  320. };
  321. &usb2 {
  322. status = "okay";
  323. };
  324. &usb2_hs_phy {
  325. status = "okay";
  326. };