qcom-ipq4028-wpj428.dts 5.9 KB

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  1. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  2. * Copyright (c) 2017, Christian Mehlis <[email protected]>
  3. * Copyright (c) 2017-2018, Sven Eckelmann <[email protected]>
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. #include "qcom-ipq4019.dtsi"
  19. #include <dt-bindings/gpio/gpio.h>
  20. #include <dt-bindings/input/input.h>
  21. #include <dt-bindings/soc/qcom,tcsr.h>
  22. / {
  23. model = "Compex WPJ428";
  24. compatible = "compex,wpj428";
  25. chosen {
  26. /*
  27. * There's a chance that SPI reads fail even though the data itself is alright.
  28. * The read result is cached and squashfs can't recover.
  29. * Just panic when that happens and hope that next time it doesn't.
  30. */
  31. bootargs-append = " rootflags=errors=panic";
  32. };
  33. soc {
  34. rng@22000 {
  35. status = "okay";
  36. };
  37. mdio@90000 {
  38. status = "okay";
  39. pinctrl-0 = <&mdio_pins>;
  40. pinctrl-names = "default";
  41. reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
  42. reset-delay-us = <2000>;
  43. };
  44. tcsr@194b000 {
  45. /* select hostmode */
  46. compatible = "qcom,tcsr";
  47. reg = <0x194b000 0x100>;
  48. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  49. status = "okay";
  50. };
  51. tcsr@1949000 {
  52. compatible = "qcom,tcsr";
  53. reg = <0x1949000 0x100>;
  54. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  55. };
  56. ess_tcsr@1953000 {
  57. compatible = "qcom,tcsr";
  58. reg = <0x1953000 0x1000>;
  59. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  60. };
  61. tcsr@1957000 {
  62. compatible = "qcom,tcsr";
  63. reg = <0x1957000 0x100>;
  64. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  65. };
  66. crypto@8e3a000 {
  67. status = "okay";
  68. };
  69. watchdog@b017000 {
  70. status = "okay";
  71. };
  72. };
  73. keys {
  74. compatible = "gpio-keys";
  75. reset {
  76. label = "reset";
  77. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  78. linux,code = <KEY_RESTART>;
  79. };
  80. };
  81. aliases {
  82. led-boot = &status;
  83. led-failsafe = &status;
  84. led-upgrade = &status;
  85. };
  86. leds {
  87. compatible = "gpio-leds";
  88. status: rss4 {
  89. label = "green:rss4";
  90. gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  91. };
  92. rss3 {
  93. label = "green:rss3";
  94. gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  95. };
  96. };
  97. beeper: beeper {
  98. compatible = "gpio-beeper";
  99. gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
  100. };
  101. };
  102. &tlmm {
  103. mdio_pins: mdio_pinmux {
  104. mux_1 {
  105. pins = "gpio53";
  106. function = "mdio";
  107. bias-pull-up;
  108. };
  109. mux_2 {
  110. pins = "gpio52";
  111. function = "mdc";
  112. bias-pull-up;
  113. };
  114. };
  115. serial_pins: serial_pinmux {
  116. mux {
  117. pins = "gpio60", "gpio61";
  118. function = "blsp_uart0";
  119. bias-disable;
  120. };
  121. };
  122. spi_0_pins: spi_0_pinmux {
  123. pin {
  124. function = "blsp_spi0";
  125. pins = "gpio55", "gpio56", "gpio57";
  126. drive-strength = <12>;
  127. bias-disable;
  128. };
  129. pin_cs {
  130. function = "gpio";
  131. pins = "gpio54";
  132. drive-strength = <2>;
  133. bias-disable;
  134. output-high;
  135. };
  136. };
  137. };
  138. &blsp_dma {
  139. status = "okay";
  140. };
  141. &blsp1_spi1 {
  142. pinctrl-0 = <&spi_0_pins>;
  143. pinctrl-names = "default";
  144. status = "okay";
  145. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
  146. m25p80@0 {
  147. compatible = "jedec,spi-nor";
  148. reg = <0>;
  149. spi-max-frequency = <24000000>;
  150. partitions {
  151. compatible = "fixed-partitions";
  152. #address-cells = <1>;
  153. #size-cells = <1>;
  154. partition0@0 {
  155. label = "0:SBL1";
  156. reg = <0x00000000 0x00040000>;
  157. read-only;
  158. };
  159. partition1@40000 {
  160. label = "0:MIBIB";
  161. reg = <0x00040000 0x00020000>;
  162. read-only;
  163. };
  164. partition2@60000 {
  165. label = "0:QSEE";
  166. reg = <0x00060000 0x00060000>;
  167. read-only;
  168. };
  169. partition3@c0000 {
  170. label = "0:CDT";
  171. reg = <0x000c0000 0x00010000>;
  172. read-only;
  173. };
  174. partition4@d0000 {
  175. label = "0:DDRPARAMS";
  176. reg = <0x000d0000 0x00010000>;
  177. read-only;
  178. };
  179. partition5@e0000 {
  180. label = "0:APPSBLENV"; /* uboot env*/
  181. reg = <0x000e0000 0x00010000>;
  182. read-only;
  183. };
  184. partition5@f0000 {
  185. label = "0:APPSBL"; /* uboot */
  186. reg = <0x000f0000 0x00080000>;
  187. read-only;
  188. };
  189. partition5@170000 {
  190. label = "0:ART";
  191. reg = <0x00170000 0x00010000>;
  192. read-only;
  193. nvmem-layout {
  194. compatible = "fixed-layout";
  195. #address-cells = <1>;
  196. #size-cells = <1>;
  197. macaddr_art_e010: mac-address@e010 {
  198. reg = <0xe010 0x6>;
  199. };
  200. macaddr_art_e018: mac-address@e018 {
  201. reg = <0xe018 0x6>;
  202. };
  203. precal_art_1000: precal@1000 {
  204. reg = <0x1000 0x2f20>;
  205. };
  206. precal_art_5000: precal@5000 {
  207. reg = <0x5000 0x2f20>;
  208. };
  209. };
  210. };
  211. partition6@180000 {
  212. compatible = "denx,fit";
  213. label = "firmware";
  214. reg = <0x00180000 0x01e80000>;
  215. };
  216. };
  217. };
  218. };
  219. &blsp1_uart1 {
  220. pinctrl-0 = <&serial_pins>;
  221. pinctrl-names = "default";
  222. status = "okay";
  223. };
  224. &cryptobam {
  225. status = "okay";
  226. };
  227. &gmac {
  228. status = "okay";
  229. };
  230. &switch {
  231. status = "okay";
  232. };
  233. &swport4 {
  234. status = "okay";
  235. label = "lan1";
  236. nvmem-cells = <&macaddr_art_e018>;
  237. nvmem-cell-names = "mac-address";
  238. };
  239. &swport5 {
  240. status = "okay";
  241. label = "lan2";
  242. nvmem-cells = <&macaddr_art_e010>;
  243. nvmem-cell-names = "mac-address";
  244. };
  245. &usb3 {
  246. status = "okay";
  247. };
  248. &usb3_ss_phy {
  249. status = "okay";
  250. };
  251. &usb3_hs_phy {
  252. status = "okay";
  253. };
  254. &usb2 {
  255. status = "okay";
  256. };
  257. &usb2_hs_phy {
  258. status = "okay";
  259. };
  260. &wifi0 {
  261. status = "okay";
  262. nvmem-cell-names = "pre-calibration";
  263. nvmem-cells = <&precal_art_1000>;
  264. };
  265. &wifi1 {
  266. status = "okay";
  267. nvmem-cell-names = "pre-calibration";
  268. nvmem-cells = <&precal_art_5000>;
  269. };