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- From 7acd8ef92e8789e10b5d736d73cea3b625087f26 Mon Sep 17 00:00:00 2001
- From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <[email protected]>
- Date: Wed, 8 Dec 2021 06:07:44 +0100
- Subject: [PATCH] PCI: aardvark: Add support for PME interrupts
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- Currently enabling PCI_EXP_RTSTA_PME bit in PCI_EXP_RTCTL register does
- nothing. This is because PCIe PME driver expects to receive PCIe interrupt
- defined in PCI_EXP_FLAGS_IRQ register, but aardvark hardware does not
- trigger PCIe INTx/MSI interrupt for PME event, rather it triggers custom
- aardvark interrupt which this driver is not processing yet.
- Fix this issue by handling PME interrupt in advk_pcie_handle_int() and
- chaining it to PCIe interrupt 0 with generic_handle_domain_irq() (since
- aardvark sets PCI_EXP_FLAGS_IRQ to zero). With this change PCIe PME driver
- finally starts receiving PME interrupt.
- Signed-off-by: Pali Rohár <[email protected]>
- Signed-off-by: Marek Behún <[email protected]>
- ---
- drivers/pci/controller/pci-aardvark.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
- --- a/drivers/pci/controller/pci-aardvark.c
- +++ b/drivers/pci/controller/pci-aardvark.c
- @@ -1489,6 +1489,19 @@ static void advk_pcie_handle_int(struct
- isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
- isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
-
- + /* Process PME interrupt */
- + if (isr0_status & PCIE_MSG_PM_PME_MASK) {
- + /*
- + * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ
- + * receiver by writing to the PCI_EXP_RTSTA register of emulated
- + * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,
- + * so use PCIe interrupt 0.
- + */
- + virq = irq_find_mapping(pcie->irq_domain, 0);
- + if (generic_handle_irq(virq) == -EINVAL)
- + dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
- + }
- +
- /* Process ERR interrupt */
- if (isr0_status & PCIE_ISR0_ERR_MASK) {
- advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
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