| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114 |
- From 5d6a82632eb7258c8ca49cc96c18b8b4071b6639 Mon Sep 17 00:00:00 2001
- From: Sean Wang <[email protected]>
- Date: Wed, 20 Sep 2017 17:40:16 +0800
- Subject: [PATCH 101/224] reset: mediatek: add reset controller dt-bindings
- required header for MT7622 SoC
- Add the reset controller dt-bindings exported from infracfg, pericfg,
- hifsys and ethsys which could be found on MT7622 SoC. So that we can
- reference them from within a device-tree file.
- Signed-off-by: Sean Wang <[email protected]>
- Signed-off-by: Philipp Zabel <[email protected]>
- ---
- include/dt-bindings/reset/mt7622-reset.h | 94 ++++++++++++++++++++++++++++++++
- 1 file changed, 94 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7622-reset.h
- --- /dev/null
- +++ b/include/dt-bindings/reset/mt7622-reset.h
- @@ -0,0 +1,94 @@
- +/*
- + * Copyright (c) 2017 MediaTek Inc.
- + * Author: Sean Wang <[email protected]>
- + *
- + * This program is free software; you can redistribute it and/or modify
- + * it under the terms of the GNU General Public License version 2 as
- + * published by the Free Software Foundation.
- + *
- + * This program is distributed in the hope that it will be useful,
- + * but WITHOUT ANY WARRANTY; without even the implied warranty of
- + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- + * GNU General Public License for more details.
- + */
- +
- +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
- +#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
- +
- +/* INFRACFG resets */
- +#define MT7622_INFRA_EMI_REG_RST 0
- +#define MT7622_INFRA_DRAMC0_A0_RST 1
- +#define MT7622_INFRA_APCIRQ_EINT_RST 3
- +#define MT7622_INFRA_APXGPT_RST 4
- +#define MT7622_INFRA_SCPSYS_RST 5
- +#define MT7622_INFRA_PMIC_WRAP_RST 7
- +#define MT7622_INFRA_IRRX_RST 9
- +#define MT7622_INFRA_EMI_RST 16
- +#define MT7622_INFRA_WED0_RST 17
- +#define MT7622_INFRA_DRAMC_RST 18
- +#define MT7622_INFRA_CCI_INTF_RST 19
- +#define MT7622_INFRA_TRNG_RST 21
- +#define MT7622_INFRA_SYSIRQ_RST 22
- +#define MT7622_INFRA_WED1_RST 25
- +
- +/* PERICFG Subsystem resets */
- +#define MT7622_PERI_UART0_SW_RST 0
- +#define MT7622_PERI_UART1_SW_RST 1
- +#define MT7622_PERI_UART2_SW_RST 2
- +#define MT7622_PERI_UART3_SW_RST 3
- +#define MT7622_PERI_UART4_SW_RST 4
- +#define MT7622_PERI_BTIF_SW_RST 6
- +#define MT7622_PERI_PWM_SW_RST 8
- +#define MT7622_PERI_AUXADC_SW_RST 10
- +#define MT7622_PERI_DMA_SW_RST 11
- +#define MT7622_PERI_IRTX_SW_RST 13
- +#define MT7622_PERI_NFI_SW_RST 14
- +#define MT7622_PERI_THERM_SW_RST 16
- +#define MT7622_PERI_MSDC0_SW_RST 19
- +#define MT7622_PERI_MSDC1_SW_RST 20
- +#define MT7622_PERI_I2C0_SW_RST 22
- +#define MT7622_PERI_I2C1_SW_RST 23
- +#define MT7622_PERI_I2C2_SW_RST 24
- +#define MT7622_PERI_SPI0_SW_RST 33
- +#define MT7622_PERI_SPI1_SW_RST 34
- +#define MT7622_PERI_FLASHIF_SW_RST 36
- +
- +/* TOPRGU resets */
- +#define MT7622_TOPRGU_INFRA_RST 0
- +#define MT7622_TOPRGU_ETHDMA_RST 1
- +#define MT7622_TOPRGU_DDRPHY_RST 6
- +#define MT7622_TOPRGU_INFRA_AO_RST 8
- +#define MT7622_TOPRGU_CONN_RST 9
- +#define MT7622_TOPRGU_APMIXED_RST 10
- +#define MT7622_TOPRGU_CONN_MCU_RST 12
- +
- +/* PCIe/SATA Subsystem resets */
- +#define MT7622_SATA_PHY_REG_RST 12
- +#define MT7622_SATA_PHY_SW_RST 13
- +#define MT7622_SATA_AXI_BUS_RST 15
- +#define MT7622_PCIE1_CORE_RST 19
- +#define MT7622_PCIE1_MMIO_RST 20
- +#define MT7622_PCIE1_HRST 21
- +#define MT7622_PCIE1_USER_RST 22
- +#define MT7622_PCIE1_PIPE_RST 23
- +#define MT7622_PCIE0_CORE_RST 27
- +#define MT7622_PCIE0_MMIO_RST 28
- +#define MT7622_PCIE0_HRST 29
- +#define MT7622_PCIE0_USER_RST 30
- +#define MT7622_PCIE0_PIPE_RST 31
- +
- +/* SSUSB Subsystem resets */
- +#define MT7622_SSUSB_PHY_PWR_RST 3
- +#define MT7622_SSUSB_MAC_PWR_RST 4
- +
- +/* ETHSYS Subsystem resets */
- +#define MT7622_ETHSYS_SYS_RST 0
- +#define MT7622_ETHSYS_MCM_RST 2
- +#define MT7622_ETHSYS_HSDMA_RST 5
- +#define MT7622_ETHSYS_FE_RST 6
- +#define MT7622_ETHSYS_GMAC_RST 23
- +#define MT7622_ETHSYS_EPHY_RST 24
- +#define MT7622_ETHSYS_CRYPTO_RST 29
- +#define MT7622_ETHSYS_PPE_RST 31
- +
- +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */
|
