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0158-mmc-mediatek-add-latch-ck-support.patch 1.7 KB

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  1. From de14d1d0dc7ecf5c3e7e2a591b4f14e688fa52e6 Mon Sep 17 00:00:00 2001
  2. From: Chaotian Jing <[email protected]>
  3. Date: Mon, 16 Oct 2017 09:46:37 +0800
  4. Subject: [PATCH 158/224] mmc: mediatek: add latch-ck support
  5. some platform(eg.mt2701) does not support "stop clk fix", in
  6. this case, need set correct latch-ck to avoid crc error caused
  7. by stop clock block-internally.
  8. Signed-off-by: Chaotian Jing <[email protected]>
  9. Tested-by: Sean Wang <[email protected]>
  10. Signed-off-by: Ulf Hansson <[email protected]>
  11. ---
  12. drivers/mmc/host/mtk-sd.c | 6 ++++++
  13. 1 file changed, 6 insertions(+)
  14. --- a/drivers/mmc/host/mtk-sd.c
  15. +++ b/drivers/mmc/host/mtk-sd.c
  16. @@ -378,6 +378,7 @@ struct msdc_host {
  17. u32 sclk; /* SD/MS bus clock frequency */
  18. unsigned char timing;
  19. bool vqmmc_enabled;
  20. + u32 latch_ck;
  21. u32 hs400_ds_delay;
  22. u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
  23. u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
  24. @@ -1661,6 +1662,8 @@ static int msdc_tune_data(struct mmc_hos
  25. u32 tune_reg = host->dev_comp->pad_tune_reg;
  26. int i, ret;
  27. + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
  28. + host->latch_ck);
  29. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
  30. sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
  31. for (i = 0 ; i < PAD_DELAY_MAX; i++) {
  32. @@ -1773,6 +1776,9 @@ static const struct mmc_host_ops mt_msdc
  33. static void msdc_of_property_parse(struct platform_device *pdev,
  34. struct msdc_host *host)
  35. {
  36. + of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
  37. + &host->latch_ck);
  38. +
  39. of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
  40. &host->hs400_ds_delay);