0184-ASoC-mediatek-add-some-core-clocks-for-MT2701-AFE.patch 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293
  1. From e0e3768b73daae674c69db1f71718894274b7bfc Mon Sep 17 00:00:00 2001
  2. From: Ryder Lee <[email protected]>
  3. Date: Thu, 4 Jan 2018 15:44:07 +0800
  4. Subject: [PATCH 184/224] ASoC: mediatek: add some core clocks for MT2701 AFE
  5. Add three core clocks for MT2701 AFE.
  6. Signed-off-by: Ryder Lee <[email protected]>
  7. Signed-off-by: Mark Brown <[email protected]>
  8. ---
  9. sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c | 30 ++++++++++++++++++++++-
  10. sound/soc/mediatek/mt2701/mt2701-afe-common.h | 3 +++
  11. 2 files changed, 32 insertions(+), 1 deletion(-)
  12. --- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  13. +++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
  14. @@ -18,8 +18,11 @@
  15. #include "mt2701-afe-clock-ctrl.h"
  16. static const char *const base_clks[] = {
  17. + [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
  18. [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
  19. [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
  20. + [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
  21. + [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
  22. [MT2701_AUDSYS_AFE] = "audio_afe_pd",
  23. [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
  24. [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
  25. @@ -169,10 +172,26 @@ static int mt2701_afe_enable_audsys(stru
  26. struct mt2701_afe_private *afe_priv = afe->platform_priv;
  27. int ret;
  28. - ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  29. + /* Enable infra clock gate */
  30. + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  31. if (ret)
  32. return ret;
  33. + /* Enable top a1sys clock gate */
  34. + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  35. + if (ret)
  36. + goto err_a1sys;
  37. +
  38. + /* Enable top a2sys clock gate */
  39. + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  40. + if (ret)
  41. + goto err_a2sys;
  42. +
  43. + /* Internal clock gates */
  44. + ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  45. + if (ret)
  46. + goto err_afe;
  47. +
  48. ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  49. if (ret)
  50. goto err_audio_a1sys;
  51. @@ -193,6 +212,12 @@ err_audio_a2sys:
  52. clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  53. err_audio_a1sys:
  54. clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  55. +err_afe:
  56. + clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  57. +err_a2sys:
  58. + clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  59. +err_a1sys:
  60. + clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  61. return ret;
  62. }
  63. @@ -205,6 +230,9 @@ static void mt2701_afe_disable_audsys(st
  64. clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
  65. clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
  66. clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
  67. + clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
  68. + clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
  69. + clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
  70. }
  71. int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
  72. --- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  73. +++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
  74. @@ -61,8 +61,11 @@ enum {
  75. };
  76. enum audio_base_clock {
  77. + MT2701_INFRA_SYS_AUDIO,
  78. MT2701_TOP_AUD_MCLK_SRC0,
  79. MT2701_TOP_AUD_MCLK_SRC1,
  80. + MT2701_TOP_AUD_A1SYS,
  81. + MT2701_TOP_AUD_A2SYS,
  82. MT2701_AUDSYS_AFE,
  83. MT2701_AUDSYS_AFE_CONN,
  84. MT2701_AUDSYS_A1SYS,