qcom-ipq4018-ap120c-ac.dts 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "ALFA Network AP120C-AC";
  9. compatible = "alfa-network,ap120c-ac";
  10. aliases {
  11. led-boot = &status;
  12. led-failsafe = &status;
  13. led-running = &status;
  14. led-upgrade = &status;
  15. ethernet1 = &swport5;
  16. };
  17. keys {
  18. compatible = "gpio-keys";
  19. reset {
  20. label = "reset";
  21. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  22. linux,code = <KEY_RESTART>;
  23. };
  24. };
  25. leds {
  26. compatible = "gpio-leds";
  27. status: status {
  28. function = LED_FUNCTION_STATUS;
  29. color = <LED_COLOR_ID_BLUE>;
  30. gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
  31. default-state = "keep";
  32. };
  33. wan {
  34. function = LED_FUNCTION_WAN;
  35. color = <LED_COLOR_ID_AMBER>;
  36. gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
  37. };
  38. wlan2g {
  39. label = "green:wlan2g";
  40. gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  41. linux,default-trigger = "phy0tpt";
  42. };
  43. wlan5g {
  44. label = "red:wlan5g";
  45. gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  46. linux,default-trigger = "phy1tpt";
  47. };
  48. };
  49. soc {
  50. rng@22000 {
  51. status = "okay";
  52. };
  53. mdio@90000 {
  54. status = "okay";
  55. pinctrl-0 = <&mdio_pins>;
  56. pinctrl-names = "default";
  57. };
  58. counter@4a1000 {
  59. compatible = "qcom,qca-gcnt";
  60. reg = <0x4a1000 0x4>;
  61. };
  62. tcsr@1949000 {
  63. compatible = "qcom,tcsr";
  64. reg = <0x1949000 0x100>;
  65. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  66. };
  67. tcsr@194b000 {
  68. compatible = "qcom,tcsr";
  69. reg = <0x194b000 0x100>;
  70. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  71. };
  72. ess_tcsr@1953000 {
  73. compatible = "qcom,tcsr";
  74. reg = <0x1953000 0x1000>;
  75. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  76. };
  77. tcsr@1957000 {
  78. compatible = "qcom,tcsr";
  79. reg = <0x1957000 0x100>;
  80. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  81. };
  82. usb2@60f8800 {
  83. status = "okay";
  84. };
  85. usb3@8af8800 {
  86. status = "okay";
  87. dwc3@8a00000 {
  88. phys = <&usb3_hs_phy>;
  89. phy-names = "usb2-phy";
  90. };
  91. };
  92. crypto@8e3a000 {
  93. status = "okay";
  94. };
  95. watchdog@b017000 {
  96. status = "okay";
  97. };
  98. };
  99. };
  100. &blsp_dma {
  101. status = "okay";
  102. };
  103. &blsp1_i2c3 {
  104. status = "okay";
  105. pinctrl-0 = <&i2c0_pins>;
  106. pinctrl-names = "default";
  107. tpm@29 {
  108. compatible = "atmel,at97sc3204t";
  109. reg = <0x29>;
  110. };
  111. };
  112. &blsp1_spi1 {
  113. status = "okay";
  114. pinctrl-0 = <&spi0_pins>;
  115. pinctrl-names = "default";
  116. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
  117. <&tlmm 4 GPIO_ACTIVE_HIGH>;
  118. flash@0 {
  119. compatible = "jedec,spi-nor";
  120. reg = <0>;
  121. spi-max-frequency = <24000000>;
  122. partitions {
  123. compatible = "fixed-partitions";
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. partition@0 {
  127. label = "SBL1";
  128. reg = <0x00000000 0x00040000>;
  129. read-only;
  130. };
  131. partition@40000 {
  132. label = "MIBIB";
  133. reg = <0x00040000 0x00020000>;
  134. read-only;
  135. };
  136. partition@60000 {
  137. label = "QSEE";
  138. reg = <0x00060000 0x00060000>;
  139. read-only;
  140. };
  141. partition@c0000 {
  142. label = "CDT";
  143. reg = <0x000c0000 0x00010000>;
  144. read-only;
  145. };
  146. partition@d0000 {
  147. label = "DDRPARAMS";
  148. reg = <0x000d0000 0x00010000>;
  149. read-only;
  150. };
  151. partition@e0000 {
  152. label = "APPSBLENV";
  153. reg = <0x000e0000 0x00010000>;
  154. };
  155. partition@f0000 {
  156. label = "APPSBL";
  157. reg = <0x000f0000 0x00080000>;
  158. read-only;
  159. };
  160. partition@170000 {
  161. label = "ART";
  162. reg = <0x00170000 0x00010000>;
  163. read-only;
  164. nvmem-layout {
  165. compatible = "fixed-layout";
  166. #address-cells = <1>;
  167. #size-cells = <1>;
  168. precal_art_1000: precal@1000 {
  169. reg = <0x1000 0x2f20>;
  170. };
  171. precal_art_5000: precal@5000 {
  172. reg = <0x5000 0x2f20>;
  173. };
  174. };
  175. };
  176. partition@180000 {
  177. label = "priv_data1";
  178. reg = <0x00180000 0x00010000>;
  179. read-only;
  180. };
  181. partition@190000 {
  182. label = "priv_data2";
  183. reg = <0x00190000 0x00010000>;
  184. read-only;
  185. };
  186. };
  187. };
  188. nand@1 {
  189. compatible = "spi-nand";
  190. reg = <1>;
  191. spi-max-frequency = <24000000>;
  192. partitions {
  193. compatible = "fixed-partitions";
  194. #address-cells = <1>;
  195. #size-cells = <1>;
  196. partition@0 {
  197. label = "rootfs1";
  198. reg = <0x00000000 0x04000000>;
  199. };
  200. partition@4000000 {
  201. label = "rootfs2";
  202. reg = <0x04000000 0x04000000>;
  203. };
  204. };
  205. };
  206. };
  207. &blsp1_uart1 {
  208. status = "okay";
  209. pinctrl-0 = <&serial0_pins>;
  210. pinctrl-names = "default";
  211. };
  212. &cryptobam {
  213. status = "okay";
  214. };
  215. &ethphy4 {
  216. gpio-controller;
  217. #gpio-cells = <2>;
  218. };
  219. &tlmm {
  220. i2c0_pins: i2c0_pinmux {
  221. mux_i2c {
  222. function = "blsp_i2c0";
  223. pins = "gpio58", "gpio59";
  224. drive-strength = <16>;
  225. bias-disable;
  226. };
  227. };
  228. mdio_pins: mdio_pinmux {
  229. mux_mdio {
  230. pins = "gpio53";
  231. function = "mdio";
  232. bias-pull-up;
  233. };
  234. mux_mdc {
  235. pins = "gpio52";
  236. function = "mdc";
  237. bias-pull-up;
  238. };
  239. };
  240. serial0_pins: serial0_pinmux {
  241. mux_uart {
  242. pins = "gpio60", "gpio61";
  243. function = "blsp_uart0";
  244. bias-disable;
  245. };
  246. };
  247. spi0_pins: spi0_pinmux {
  248. mux_spi {
  249. function = "blsp_spi0";
  250. pins = "gpio55", "gpio56", "gpio57";
  251. drive-strength = <12>;
  252. bias-disable;
  253. };
  254. mux_cs {
  255. function = "gpio";
  256. pins = "gpio54", "gpio4";
  257. drive-strength = <2>;
  258. bias-disable;
  259. output-high;
  260. };
  261. };
  262. };
  263. &usb2_hs_phy {
  264. status = "okay";
  265. };
  266. &usb3_hs_phy {
  267. status = "okay";
  268. };
  269. &gmac {
  270. status = "okay";
  271. };
  272. &switch {
  273. status = "okay";
  274. };
  275. &swport4 {
  276. status = "okay";
  277. label = "lan";
  278. };
  279. &swport5 {
  280. status = "okay";
  281. };
  282. &wifi0 {
  283. status = "okay";
  284. nvmem-cell-names = "pre-calibration";
  285. nvmem-cells = <&precal_art_1000>;
  286. };
  287. &wifi1 {
  288. status = "okay";
  289. qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
  290. nvmem-cell-names = "pre-calibration";
  291. nvmem-cells = <&precal_art_5000>;
  292. };