openwrt/target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts

// SPDX-License-Identifier: GPL-2.0-only OR MIT

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,tcsr.h>

/ {
	model = "EZVIZ CS-W3-WD1200G EUP";
	compatible = "ezviz,cs-w3-wd1200g-eup";

	aliases {
		led-boot = &led_status_green;
		led-failsafe = &led_status_red;
		led-running = &led_status_blue;
		led-upgrade = &led_status_green;
	};

	soc {
		rng@22000 {
			status = "okay";
		};

		mdio@90000 {
			status = "okay";
			pinctrl-0 = <&mdio_pins>;
			pinctrl-names = "default";
			reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
			reset-delay-us = <5000>;
		};

		tcsr@1949000 {
			compatible = "qcom,tcsr";
			reg = <0x1949000 0x100>;
			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
		};

		tcsr@194b000 {
			compatible = "qcom,tcsr";
			reg = <0x194b000 0x100>;
			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
		};

		ess_tcsr@1953000 {
			compatible = "qcom,tcsr";
			reg = <0x1953000 0x1000>;
			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
		};

		tcsr@1957000 {
			compatible = "qcom,tcsr";
			reg = <0x1957000 0x100>;
			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
		};

		crypto@8e3a000 {
			status = "okay";
		};

		watchdog@b017000 {
			status = "okay";
		};
	};

	leds {
		compatible = "gpio-leds";

		led_status_red: status_red {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
		};

		led_status_green: status_green {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
		};

		led_status_blue: status_blue {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_BLUE>;
			gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};
};

&tlmm {
	serial_pins: serial_pinmux {
		mux {
			pins = "gpio60", "gpio61";
			function = "blsp_uart0";
			bias-disable;
		};
	};

	mdio_pins: mdio_pinmux {
		mux_1 {
			pins = "gpio53";
			function = "mdio";
			bias-pull-up;
		};

		mux_2 {
			pins = "gpio52";
			function = "mdc";
			bias-pull-up;
		};
	};

	spi_0_pins: spi_0_pinmux {
		pin {
			function = "blsp_spi0";
			pins = "gpio55", "gpio56", "gpio57";
			drive-strength = <12>;
			bias-disable;
		};
		pin_cs {
			function = "gpio";
			pins = "gpio54";
			drive-strength = <2>;
			bias-disable;
			output-high;
		};
	};
};

&blsp_dma {
	status = "okay";
};

&blsp1_spi1 {
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	status = "okay";
	cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <24000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition0@0 {
				label = "SBL1";
				reg = <0x00000000 0x00040000>;
				read-only;
			};

			partition1@40000 {
				label = "MIBIB";
				reg = <0x00040000 0x00020000>;
				read-only;
			};

			partition2@60000 {
				label = "QSEE";
				reg = <0x00060000 0x00060000>;
				read-only;
			};

			partition3@c0000 {
				label = "CDT";
				reg = <0x000c0000 0x00010000>;
				read-only;
			};

			partition4@d0000 {
				label = "DDRPARAMS";
				reg = <0x000d0000 0x00010000>;
				read-only;
			};

			partition5@E0000 {
				label = "APPSBLENV";
				reg = <0x000e0000 0x00010000>;
				read-only;
			};

			partition6@F0000 {
				label = "APPSBL";
				reg = <0x000f0000 0x00080000>;
				read-only;
			};

			partition7@170000 {
				label = "ART";
				reg = <0x00170000 0x00010000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_art_0: macaddr@0 {
						reg = <0x0 0x6>;
					};

					macaddr_art_6: macaddr@6 {
						reg = <0x6 0x6>;
					};

					precal_art_1000: precal@1000 {
						reg = <0x1000 0x2f20>;
					};

					precal_art_5000: precal@5000 {
						reg = <0x5000 0x2f20>;
					};
				};
			};

			partition9@580000 {
				compatible = "denx,fit";
				label = "firmware";
				reg = <0x00180000 0x00e80000>;
			};
		};
	};
};

&blsp1_uart1 {
	pinctrl-0 = <&serial_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&cryptobam {
	status = "okay";
};

&gmac {
	status = "okay";
	nvmem-cells = <&macaddr_art_0>;
	nvmem-cell-names = "mac-address";
};

&switch {
	status = "okay";
};

&swport2 {
	status = "okay";
	label = "lan3";
};

&swport3 {
	status = "okay";
	label = "lan2";
};

&swport4 {
	status = "okay";
	label = "lan1";
};

&swport5 {
	status = "okay";
	label = "wan";
	nvmem-cells = <&macaddr_art_6>;
	nvmem-cell-names = "mac-address";
};

&ethphy0 {
	status = "disabled";
};

&wifi0 {
	status = "okay";
	qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
	nvmem-cell-names = "pre-calibration";
	nvmem-cells = <&precal_art_1000>;
};

&wifi1 {
	status = "okay";
	qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
	nvmem-cell-names = "pre-calibration";
	nvmem-cells = <&precal_art_5000>;
};