qcom-ipq4018-ea6350v3.dts 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "Linksys EA6350v3";
  9. compatible = "linksys,ea6350v3";
  10. aliases {
  11. led-boot = &power;
  12. led-failsafe = &power;
  13. led-running = &power;
  14. led-upgrade = &power;
  15. };
  16. soc {
  17. rng@22000 {
  18. status = "okay";
  19. };
  20. mdio@90000 {
  21. status = "okay";
  22. };
  23. tcsr@1949000 {
  24. compatible = "qcom,tcsr";
  25. reg = <0x1949000 0x100>;
  26. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  27. };
  28. tcsr@194b000 {
  29. compatible = "qcom,tcsr";
  30. reg = <0x194b000 0x100>;
  31. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  32. };
  33. ess_tcsr@1953000 {
  34. compatible = "qcom,tcsr";
  35. reg = <0x1953000 0x1000>;
  36. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  37. };
  38. tcsr@1957000 {
  39. compatible = "qcom,tcsr";
  40. reg = <0x1957000 0x100>;
  41. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  42. };
  43. usb2@60f8800 {
  44. status = "okay";
  45. };
  46. usb3@8af8800 {
  47. status = "okay";
  48. };
  49. crypto@8e3a000 {
  50. status = "okay";
  51. };
  52. watchdog@b017000 {
  53. status = "okay";
  54. };
  55. };
  56. keys {
  57. compatible = "gpio-keys";
  58. reset {
  59. label = "reset";
  60. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  61. linux,code = <KEY_RESTART>;
  62. };
  63. wps {
  64. label = "wps";
  65. gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  66. linux,code = <KEY_WPS_BUTTON>;
  67. };
  68. };
  69. leds {
  70. compatible = "gpio-leds";
  71. power: status {
  72. function = LED_FUNCTION_STATUS;
  73. color = <LED_COLOR_ID_GREEN>;
  74. gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  75. };
  76. };
  77. };
  78. &blsp1_uart1 {
  79. pinctrl-0 = <&serial_pins>;
  80. pinctrl-names = "default";
  81. status = "okay";
  82. };
  83. &cryptobam {
  84. status = "okay";
  85. };
  86. &gmac {
  87. status = "okay";
  88. };
  89. &switch {
  90. status = "okay";
  91. };
  92. &swport1 {
  93. status = "okay";
  94. };
  95. &swport2 {
  96. status = "okay";
  97. };
  98. &swport3 {
  99. status = "okay";
  100. };
  101. &swport4 {
  102. status = "okay";
  103. };
  104. &swport5 {
  105. status = "okay";
  106. };
  107. &wifi0 {
  108. status = "okay";
  109. nvmem-cell-names = "pre-calibration";
  110. nvmem-cells = <&precal_art_1000>;
  111. qcom,ath10k-calibration-variant = "linksys-ea6350v3";
  112. };
  113. &wifi1 {
  114. status = "okay";
  115. nvmem-cell-names = "pre-calibration";
  116. nvmem-cells = <&precal_art_5000>;
  117. qcom,ath10k-calibration-variant = "linksys-ea6350v3";
  118. };
  119. &blsp_dma {
  120. status = "okay";
  121. };
  122. &tlmm {
  123. serial_pins: serial_pinmux {
  124. mux {
  125. pins = "gpio60", "gpio61";
  126. function = "blsp_uart0";
  127. bias-disable;
  128. };
  129. };
  130. spi_0_pins: spi_0_pinmux {
  131. mux {
  132. function = "blsp_spi0";
  133. pins = "gpio55", "gpio56", "gpio57";
  134. drive-strength = <12>;
  135. bias-disable;
  136. };
  137. mux_cs {
  138. function = "gpio";
  139. pins = "gpio54", "gpio59";
  140. drive-strength = <2>;
  141. bias-disable;
  142. output-high;
  143. };
  144. };
  145. };
  146. &blsp1_spi1 { /* BLSP1 QUP1 */
  147. pinctrl-0 = <&spi_0_pins>;
  148. pinctrl-names = "default";
  149. status = "okay";
  150. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
  151. <&tlmm 59 GPIO_ACTIVE_HIGH>;
  152. flash@0 {
  153. compatible = "jedec,spi-nor";
  154. reg = <0>;
  155. spi-max-frequency = <24000000>;
  156. partitions {
  157. compatible = "fixed-partitions";
  158. #address-cells = <1>;
  159. #size-cells = <1>;
  160. SBL1@0 {
  161. label = "SBL1";
  162. reg = <0x00000000 0x00040000>;
  163. read-only;
  164. };
  165. MBIB@40000 {
  166. label = "MIBIB";
  167. reg = <0x00040000 0x00020000>;
  168. read-only;
  169. };
  170. QSEE@60000 {
  171. label = "QSEE";
  172. reg = <0x00060000 0x00060000>;
  173. read-only;
  174. };
  175. CDT@c0000 {
  176. label = "CDT";
  177. reg = <0x000c0000 0x00010000>;
  178. read-only;
  179. };
  180. APPSBLENV@d0000 {
  181. label = "APPSBLENV";
  182. reg = <0x000d0000 0x00010000>;
  183. read-only;
  184. };
  185. APPSBL@e0000 {
  186. label = "APPSBL"; /* uboot */
  187. reg = <0x000e0000 0x00080000>;
  188. read-only;
  189. };
  190. ART@160000 {
  191. label = "ART";
  192. reg = <0x00160000 0x00010000>;
  193. read-only;
  194. nvmem-layout {
  195. compatible = "fixed-layout";
  196. #address-cells = <1>;
  197. #size-cells = <1>;
  198. precal_art_1000: precal@1000 {
  199. reg = <0x1000 0x2f20>;
  200. };
  201. precal_art_5000: precal@5000 {
  202. reg = <0x5000 0x2f20>;
  203. };
  204. };
  205. };
  206. u_env@170000 {
  207. label = "u_env";
  208. reg = <0x00170000 0x00020000>;
  209. };
  210. s_env@190000 {
  211. label = "s_env";
  212. reg = <0x00190000 0x00020000>;
  213. };
  214. devinfo@1b0000 {
  215. label = "devinfo";
  216. reg = <0x001b0000 0x00010000>;
  217. };
  218. /* 0x001c0000 - 0x00200000 unused */
  219. };
  220. };
  221. flash@1 {
  222. status = "okay";
  223. compatible = "spi-nand";
  224. reg = <1>;
  225. spi-max-frequency = <24000000>;
  226. partitions {
  227. compatible = "fixed-partitions";
  228. #address-cells = <1>;
  229. #size-cells = <1>;
  230. kernel@0 {
  231. label = "kernel";
  232. reg = <0x00000000 0x02800000>;
  233. };
  234. rootfs@500000 {
  235. label = "rootfs";
  236. reg = <0x00500000 0x02300000>;
  237. };
  238. alt_kernel@2800000 {
  239. label = "alt_kernel";
  240. reg = <0x02800000 0x02800000>;
  241. };
  242. alt_rootfs@2d00000 {
  243. label = "alt_rootfs";
  244. reg = <0x02d00000 0x02300000>;
  245. };
  246. sysdiag@5000000 {
  247. label = "sysdiag";
  248. reg = <0x05000000 0x00100000>;
  249. };
  250. syscfg@5100000 {
  251. label = "syscfg";
  252. reg = <0x05100000 0x02F00000>;
  253. };
  254. /* 0x00000000 - 0x08000000: 128 MiB */
  255. };
  256. };
  257. };
  258. &usb3_ss_phy {
  259. status = "okay";
  260. };
  261. &usb3_hs_phy {
  262. status = "okay";
  263. };
  264. &usb2_hs_phy {
  265. status = "okay";
  266. };