qcom-ipq4018-ecw5211.dts 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "Edgecore ECW5211";
  9. compatible = "edgecore,ecw5211";
  10. aliases {
  11. led-boot = &led_power;
  12. led-failsafe = &led_power;
  13. led-running = &led_power;
  14. led-upgrade = &led_power;
  15. ethernet0 = &swport5;
  16. ethernet1 = &gmac;
  17. };
  18. chosen {
  19. bootargs-append = " root=/dev/ubiblock0_1";
  20. };
  21. keys {
  22. compatible = "gpio-keys";
  23. reset {
  24. label = "reset";
  25. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  26. linux,code = <KEY_RESTART>;
  27. };
  28. };
  29. leds {
  30. compatible = "gpio-leds";
  31. led_power: power {
  32. function = LED_FUNCTION_POWER;
  33. color = <LED_COLOR_ID_YELLOW>;
  34. gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
  35. };
  36. wlan2g {
  37. label = "green:wlan2g";
  38. gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  39. linux,default-trigger = "phy0tpt";
  40. };
  41. wlan5g {
  42. label = "green:wlan5g";
  43. gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  44. linux,default-trigger = "phy1tpt";
  45. };
  46. };
  47. soc {
  48. rng@22000 {
  49. status = "okay";
  50. };
  51. counter@4a1000 {
  52. compatible = "qcom,qca-gcnt";
  53. reg = <0x4a1000 0x4>;
  54. };
  55. tcsr@1949000 {
  56. compatible = "qcom,tcsr";
  57. reg = <0x1949000 0x100>;
  58. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  59. };
  60. tcsr@194b000 {
  61. compatible = "qcom,tcsr";
  62. reg = <0x194b000 0x100>;
  63. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  64. };
  65. ess_tcsr@1953000 {
  66. compatible = "qcom,tcsr";
  67. reg = <0x1953000 0x1000>;
  68. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  69. };
  70. tcsr@1957000 {
  71. compatible = "qcom,tcsr";
  72. reg = <0x1957000 0x100>;
  73. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  74. };
  75. usb2@60f8800 {
  76. status = "okay";
  77. };
  78. usb3@8af8800 {
  79. status = "okay";
  80. dwc3@8a00000 {
  81. phys = <&usb3_hs_phy>;
  82. phy-names = "usb2-phy";
  83. };
  84. };
  85. crypto@8e3a000 {
  86. status = "okay";
  87. };
  88. watchdog@b017000 {
  89. status = "okay";
  90. };
  91. };
  92. };
  93. &tlmm {
  94. mdio_pins: mdio_pinmux {
  95. mux_mdio {
  96. pins = "gpio53";
  97. function = "mdio";
  98. bias-pull-up;
  99. };
  100. mux_mdc {
  101. pins = "gpio52";
  102. function = "mdc";
  103. bias-pull-up;
  104. };
  105. };
  106. serial_pins: serial_pinmux {
  107. mux {
  108. pins = "gpio60", "gpio61";
  109. function = "blsp_uart0";
  110. bias-disable;
  111. };
  112. };
  113. spi0_pins: spi0_pinmux {
  114. pin {
  115. function = "blsp_spi0";
  116. pins = "gpio55", "gpio56", "gpio57";
  117. drive-strength = <2>;
  118. bias-disable;
  119. };
  120. pin_cs {
  121. function = "gpio";
  122. pins = "gpio54", "gpio4";
  123. drive-strength = <2>;
  124. bias-disable;
  125. output-high;
  126. };
  127. };
  128. i2c0_pins: i2c0_pinmux {
  129. mux_i2c {
  130. function = "blsp_i2c0";
  131. pins = "gpio58", "gpio59";
  132. drive-strength = <16>;
  133. bias-disable;
  134. };
  135. };
  136. };
  137. &blsp_dma {
  138. status = "okay";
  139. };
  140. &blsp1_spi1 {
  141. status = "okay";
  142. pinctrl-0 = <&spi0_pins>;
  143. pinctrl-names = "default";
  144. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
  145. flash@0 {
  146. compatible = "jedec,spi-nor";
  147. reg = <0>;
  148. spi-max-frequency = <24000000>;
  149. partitions {
  150. compatible = "fixed-partitions";
  151. #address-cells = <1>;
  152. #size-cells = <1>;
  153. partition@0 {
  154. label = "0:SBL1";
  155. reg = <0x00000000 0x00040000>;
  156. read-only;
  157. };
  158. partition@40000 {
  159. label = "0:MIBIB";
  160. reg = <0x00040000 0x00020000>;
  161. read-only;
  162. };
  163. partition@60000 {
  164. label = "0:QSEE";
  165. reg = <0x00060000 0x00060000>;
  166. read-only;
  167. };
  168. partition@c0000 {
  169. label = "0:CDT";
  170. reg = <0x000c0000 0x00010000>;
  171. read-only;
  172. };
  173. partition@d0000 {
  174. label = "0:DDRPARAMS";
  175. reg = <0x000d0000 0x00010000>;
  176. read-only;
  177. };
  178. partition@e0000 {
  179. label = "0:APPSBLENV"; /* uboot env */
  180. reg = <0x000e0000 0x00010000>;
  181. };
  182. partition@f0000 {
  183. label = "0:APPSBL"; /* uboot */
  184. reg = <0x000f0000 0x00080000>;
  185. read-only;
  186. };
  187. partition@170000 {
  188. label = "0:ART";
  189. reg = <0x00170000 0x00010000>;
  190. read-only;
  191. nvmem-layout {
  192. compatible = "fixed-layout";
  193. #address-cells = <1>;
  194. #size-cells = <1>;
  195. precal_art_1000: precal@1000 {
  196. reg = <0x1000 0x2f20>;
  197. };
  198. precal_art_5000: precal@5000 {
  199. reg = <0x5000 0x2f20>;
  200. };
  201. };
  202. };
  203. };
  204. };
  205. flash@1 {
  206. compatible = "spi-nand";
  207. reg = <1>;
  208. spi-max-frequency = <24000000>;
  209. partitions {
  210. compatible = "fixed-partitions";
  211. #address-cells = <1>;
  212. #size-cells = <1>;
  213. partition@0 {
  214. label = "rootfs";
  215. reg = <0x00000000 0x04000000>;
  216. };
  217. };
  218. };
  219. };
  220. &blsp1_i2c3 {
  221. status = "okay";
  222. pinctrl-0 = <&i2c0_pins>;
  223. pinctrl-names = "default";
  224. tpm@29 {
  225. compatible = "atmel,at97sc3204t";
  226. reg = <0x29>;
  227. };
  228. };
  229. &blsp1_uart1 {
  230. status = "okay";
  231. pinctrl-0 = <&serial_pins>;
  232. pinctrl-names = "default";
  233. };
  234. &cryptobam {
  235. status = "okay";
  236. };
  237. &mdio {
  238. status = "okay";
  239. pinctrl-0 = <&mdio_pins>;
  240. pinctrl-names = "default";
  241. };
  242. &gmac {
  243. status = "okay";
  244. };
  245. &switch {
  246. status = "okay";
  247. };
  248. &swport4 {
  249. status = "okay";
  250. label = "lan";
  251. };
  252. &swport5 {
  253. status = "okay";
  254. };
  255. &wifi0 {
  256. status = "okay";
  257. nvmem-cell-names = "pre-calibration";
  258. nvmem-cells = <&precal_art_1000>;
  259. };
  260. &wifi1 {
  261. status = "okay";
  262. nvmem-cell-names = "pre-calibration";
  263. nvmem-cells = <&precal_art_5000>;
  264. qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
  265. };
  266. &usb3_hs_phy {
  267. status = "okay";
  268. };
  269. &usb2_hs_phy {
  270. status = "okay";
  271. };