qcom-ipq4018-ex61x0v2.dtsi 6.5 KB

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  1. /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
  2. * Copyright (c) 2018, David Bauer <[email protected]>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. *
  16. */
  17. #include "qcom-ipq4019.dtsi"
  18. #include <dt-bindings/gpio/gpio.h>
  19. #include <dt-bindings/input/input.h>
  20. #include <dt-bindings/leds/common.h>
  21. #include <dt-bindings/soc/qcom,tcsr.h>
  22. / {
  23. model = "Netgear EX61X0v2";
  24. compatible = "netgear,ex61x0v2";
  25. soc {
  26. rng@22000 {
  27. status = "okay";
  28. };
  29. mdio@90000 {
  30. status = "okay";
  31. };
  32. tcsr@1949000 {
  33. compatible = "qcom,tcsr";
  34. reg = <0x1949000 0x100>;
  35. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  36. };
  37. ess_tcsr@1953000 {
  38. compatible = "qcom,tcsr";
  39. reg = <0x1953000 0x1000>;
  40. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  41. };
  42. tcsr@1957000 {
  43. compatible = "qcom,tcsr";
  44. reg = <0x1957000 0x100>;
  45. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  46. };
  47. crypto@8e3a000 {
  48. status = "okay";
  49. };
  50. watchdog@b017000 {
  51. status = "okay";
  52. };
  53. };
  54. aliases {
  55. led-boot = &power_amber;
  56. led-failsafe = &power_amber;
  57. led-running = &power_green;
  58. led-upgrade = &power_amber;
  59. label-mac-device = &gmac;
  60. };
  61. keys {
  62. compatible = "gpio-keys";
  63. wps {
  64. label = "wps";
  65. gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  66. linux,code = <KEY_WPS_BUTTON>;
  67. };
  68. reset {
  69. label = "reset";
  70. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  71. linux,code = <KEY_RESTART>;
  72. };
  73. };
  74. led_spi {
  75. compatible = "spi-gpio";
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  79. mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  80. num-chipselects = <0>;
  81. led_gpio: led_gpio@0 {
  82. compatible = "fairchild,74hc595";
  83. reg = <0>;
  84. gpio-controller;
  85. #gpio-cells = <2>;
  86. registers-number = <1>;
  87. spi-max-frequency = <1000000>;
  88. };
  89. };
  90. leds {
  91. compatible = "gpio-leds";
  92. power_amber: power_amber {
  93. function = LED_FUNCTION_POWER;
  94. color = <LED_COLOR_ID_AMBER>;
  95. gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
  96. };
  97. power_green: power_green {
  98. function = LED_FUNCTION_POWER;
  99. color = <LED_COLOR_ID_GREEN>;
  100. gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
  101. };
  102. right {
  103. label = "blue:right";
  104. gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
  105. };
  106. left {
  107. label = "blue:left";
  108. gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
  109. };
  110. client_green {
  111. label = "green:client";
  112. gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
  113. };
  114. client_red {
  115. label = "red:client";
  116. gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
  117. };
  118. router_green {
  119. label = "green:router";
  120. gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
  121. };
  122. router_red {
  123. label = "red:router";
  124. gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
  125. };
  126. wps {
  127. function = LED_FUNCTION_WPS;
  128. color = <LED_COLOR_ID_GREEN>;
  129. gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
  130. };
  131. };
  132. };
  133. &tlmm {
  134. serial_pins: serial_pinmux {
  135. mux {
  136. pins = "gpio60", "gpio61";
  137. function = "blsp_uart0";
  138. bias-disable;
  139. };
  140. };
  141. spi_0_pins: spi_0_pinmux {
  142. pin {
  143. function = "blsp_spi0";
  144. pins = "gpio55", "gpio56", "gpio57";
  145. drive-strength = <12>;
  146. bias-disable;
  147. };
  148. pin_cs {
  149. function = "gpio";
  150. pins = "gpio54";
  151. drive-strength = <2>;
  152. bias-disable;
  153. output-high;
  154. };
  155. };
  156. };
  157. &blsp1_spi1 {
  158. pinctrl-0 = <&spi_0_pins>;
  159. pinctrl-names = "default";
  160. status = "okay";
  161. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
  162. mx25l12805d@0 {
  163. compatible = "jedec,spi-nor";
  164. reg = <0>;
  165. spi-max-frequency = <45000000>;
  166. partitions {
  167. compatible = "fixed-partitions";
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. partition0@0 {
  171. label = "SBL1";
  172. reg = <0x00000000 0x00040000>;
  173. read-only;
  174. };
  175. partition1@40000 {
  176. label = "MIBIB";
  177. reg = <0x00040000 0x00020000>;
  178. read-only;
  179. };
  180. partition2@60000 {
  181. label = "QSEE";
  182. reg = <0x00060000 0x00060000>;
  183. read-only;
  184. };
  185. partition3@c0000 {
  186. label = "CDT";
  187. reg = <0x000c0000 0x00010000>;
  188. read-only;
  189. };
  190. partition4@d0000 {
  191. label = "DDRPARAMS";
  192. reg = <0x000d0000 0x00010000>;
  193. read-only;
  194. };
  195. partition5@E0000 {
  196. label = "APPSBLENV";
  197. reg = <0x000e0000 0x00010000>;
  198. read-only;
  199. };
  200. partition6@F0000 {
  201. label = "APPSBL";
  202. reg = <0x000f0000 0x00080000>;
  203. read-only;
  204. };
  205. partition7@170000 {
  206. label = "ART";
  207. reg = <0x00170000 0x00010000>;
  208. read-only;
  209. nvmem-layout {
  210. compatible = "fixed-layout";
  211. #address-cells = <1>;
  212. #size-cells = <1>;
  213. precal_art_1000: precal@1000 {
  214. reg = <0x1000 0x2f20>;
  215. };
  216. precal_art_5000: precal@5000 {
  217. reg = <0x5000 0x2f20>;
  218. };
  219. };
  220. };
  221. partition8@180000 {
  222. label = "config";
  223. reg = <0x00180000 0x00010000>;
  224. read-only;
  225. };
  226. partition9@190000 {
  227. label = "pot";
  228. reg = <0x00190000 0x00010000>;
  229. read-only;
  230. };
  231. partition10@1a0000 {
  232. label = "dnidata";
  233. reg = <0x001a0000 0x00010000>;
  234. read-only;
  235. nvmem-layout {
  236. compatible = "fixed-layout";
  237. #address-cells = <1>;
  238. #size-cells = <1>;
  239. macaddr_dnidata_0: macaddr@0 {
  240. reg = <0x0 0x6>;
  241. };
  242. macaddr_dnidata_c: macaddr@c {
  243. reg = <0xc 0x6>;
  244. };
  245. };
  246. };
  247. partition11@1b0000 {
  248. compatible = "denx,fit";
  249. label = "firmware";
  250. reg = <0x001b0000 0x00e10000>;
  251. };
  252. partition12@fc0000 {
  253. label = "language";
  254. reg = <0x00fc0000 0x00040000>;
  255. read-only;
  256. };
  257. };
  258. };
  259. };
  260. &blsp1_uart1 {
  261. pinctrl-0 = <&serial_pins>;
  262. pinctrl-names = "default";
  263. status = "okay";
  264. };
  265. &blsp_dma {
  266. status = "okay";
  267. };
  268. &cryptobam {
  269. status = "okay";
  270. };
  271. &wifi0 {
  272. status = "okay";
  273. nvmem-cell-names = "pre-calibration", "mac-address";
  274. nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
  275. };
  276. &wifi1 {
  277. status = "okay";
  278. nvmem-cell-names = "pre-calibration", "mac-address";
  279. nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
  280. };
  281. &gmac {
  282. status = "okay";
  283. };
  284. &switch {
  285. status = "okay";
  286. };
  287. &swport4 {
  288. status = "okay";
  289. label = "lan";
  290. };