qcom-ipq4018-gl-ap1300.dts 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "GL.iNet GL-AP1300";
  9. compatible = "glinet,gl-ap1300";
  10. aliases {
  11. led-boot = &led_power;
  12. led-failsafe = &led_power;
  13. led-running = &led_power;
  14. led-upgrade = &led_power;
  15. };
  16. memory {
  17. device_type = "memory";
  18. reg = <0x80000000 0x10000000>;
  19. };
  20. chosen {
  21. bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  22. };
  23. soc {
  24. rng@22000 {
  25. status = "okay";
  26. };
  27. mdio@90000 {
  28. status = "okay";
  29. };
  30. tcsr@1949000 {
  31. compatible = "qcom,tcsr";
  32. reg = <0x1949000 0x100>;
  33. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  34. };
  35. tcsr@194b000 {
  36. /* select hostmode */
  37. compatible = "qcom,tcsr";
  38. reg = <0x194b000 0x100>;
  39. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  40. status = "okay";
  41. };
  42. ess_tcsr@1953000 {
  43. compatible = "qcom,tcsr";
  44. reg = <0x1953000 0x1000>;
  45. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  46. };
  47. tcsr@1957000 {
  48. compatible = "qcom,tcsr";
  49. reg = <0x1957000 0x100>;
  50. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  51. };
  52. usb2@60f8800 {
  53. status = "okay";
  54. };
  55. usb3@8af8800 {
  56. status = "okay";
  57. };
  58. crypto@8e3a000 {
  59. status = "okay";
  60. };
  61. watchdog@b017000 {
  62. status = "okay";
  63. };
  64. };
  65. keys {
  66. compatible = "gpio-keys";
  67. reset {
  68. label = "reset";
  69. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  70. linux,code = <KEY_RESTART>;
  71. };
  72. };
  73. leds {
  74. compatible = "gpio-leds";
  75. led_power: power {
  76. function = LED_FUNCTION_POWER;
  77. color = <LED_COLOR_ID_WHITE>;
  78. gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
  79. default-state = "on";
  80. };
  81. wan {
  82. function = LED_FUNCTION_WAN;
  83. color = <LED_COLOR_ID_WHITE>;
  84. gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
  85. };
  86. };
  87. };
  88. &blsp_dma {
  89. status = "okay";
  90. };
  91. &cryptobam {
  92. status = "okay";
  93. };
  94. &blsp1_spi1 {
  95. status = "okay";
  96. pinctrl-0 = <&spi0_pins>;
  97. pinctrl-names = "default";
  98. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
  99. flash@0 {
  100. status = "okay";
  101. compatible = "jedec,spi-nor";
  102. reg = <0>;
  103. spi-max-frequency = <24000000>;
  104. partitions {
  105. compatible = "fixed-partitions";
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. partition@0 {
  109. label = "SBL1";
  110. reg = <0x00000000 0x00040000>;
  111. read-only;
  112. };
  113. partition@40000 {
  114. label = "MIBIB";
  115. reg = <0x00040000 0x00020000>;
  116. read-only;
  117. };
  118. partition@60000 {
  119. label = "QSEE";
  120. reg = <0x00060000 0x00060000>;
  121. read-only;
  122. };
  123. partition@c0000 {
  124. label = "CDT";
  125. reg = <0x000c0000 0x00010000>;
  126. read-only;
  127. };
  128. partition@d0000 {
  129. label = "DDRPARAMS";
  130. reg = <0x000d0000 0x00010000>;
  131. read-only;
  132. };
  133. partition@e0000 {
  134. label = "APPSBLENV"; /* uboot env*/
  135. reg = <0x000e0000 0x00010000>;
  136. };
  137. partition@f0000 {
  138. label = "APPSBL"; /* uboot */
  139. reg = <0x000f0000 0x00080000>;
  140. read-only;
  141. };
  142. partition@170000 {
  143. label = "ART";
  144. reg = <0x00170000 0x00010000>;
  145. read-only;
  146. nvmem-layout {
  147. compatible = "fixed-layout";
  148. #address-cells = <1>;
  149. #size-cells = <1>;
  150. macaddr_art_0: mac-address@0 {
  151. reg = <0x0 0x6>;
  152. };
  153. macaddr_art_6: mac-address@6 {
  154. reg = <0x6 0x6>;
  155. };
  156. precal_art_1000: precal@1000 {
  157. reg = <0x1000 0x2f20>;
  158. };
  159. precal_art_5000: precal@5000 {
  160. reg = <0x5000 0x2f20>;
  161. };
  162. };
  163. };
  164. };
  165. };
  166. spi-nand@1 {
  167. status = "okay";
  168. compatible = "spi-nand";
  169. reg = <1>;
  170. spi-max-frequency = <24000000>;
  171. partitions {
  172. compatible = "fixed-partitions";
  173. #address-cells = <1>;
  174. #size-cells = <1>;
  175. partition@0 {
  176. label = "ubi";
  177. reg = <0x00000000 0x08000000>;
  178. };
  179. };
  180. };
  181. };
  182. &blsp1_uart1 {
  183. pinctrl-0 = <&serial_pins>;
  184. pinctrl-names = "default";
  185. status = "okay";
  186. };
  187. &tlmm {
  188. serial_pins: serial_pinmux {
  189. mux {
  190. pins = "gpio60", "gpio61";
  191. function = "blsp_uart0";
  192. bias-disable;
  193. };
  194. };
  195. spi0_pins: spi0_pinmux {
  196. mux_spi {
  197. function = "blsp_spi0";
  198. pins = "gpio55", "gpio56", "gpio57";
  199. drive-strength = <12>;
  200. bias-disable;
  201. };
  202. mux_cs {
  203. function = "gpio";
  204. pins = "gpio54", "gpio5";
  205. drive-strength = <2>;
  206. bias-disable;
  207. output-high;
  208. };
  209. };
  210. };
  211. &usb2_hs_phy {
  212. status = "okay";
  213. };
  214. &usb3_hs_phy {
  215. status = "okay";
  216. };
  217. &usb3_ss_phy {
  218. status = "okay";
  219. };
  220. &gmac {
  221. status = "okay";
  222. };
  223. &switch {
  224. status = "okay";
  225. };
  226. &swport4 {
  227. status = "okay";
  228. label = "lan";
  229. nvmem-cells = <&macaddr_art_0>;
  230. nvmem-cell-names = "mac-address";
  231. };
  232. &swport5 {
  233. status = "okay";
  234. label = "wan";
  235. nvmem-cells = <&macaddr_art_6>;
  236. nvmem-cell-names = "mac-address";
  237. };
  238. &wifi0 {
  239. status = "okay";
  240. nvmem-cell-names = "pre-calibration";
  241. nvmem-cells = <&precal_art_1000>;
  242. qcom,ath10k-calibration-variant = "GL-AP1300";
  243. };
  244. &wifi1 {
  245. status = "okay";
  246. nvmem-cell-names = "pre-calibration";
  247. nvmem-cells = <&precal_art_5000>;
  248. qcom,ath10k-calibration-variant = "GL-AP1300";
  249. };