qcom-ipq4018-mf287.dts 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2022, Pawel Dembicki <[email protected]>.
  3. // Copyright (c) 2022, Giammarco Marzano <[email protected]>.
  4. // Copyright (c) 2023, Andreas Böhler <[email protected]>
  5. #include "qcom-ipq4018-mf287_common.dtsi"
  6. / {
  7. model = "ZTE MF287";
  8. compatible = "zte,mf287";
  9. };
  10. &gpio_modem_reset {
  11. gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  12. };
  13. &key_reset {
  14. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  15. };
  16. &key_wps {
  17. gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
  18. };
  19. &led_status {
  20. gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  21. };
  22. &blsp1_spi1 {
  23. pinctrl-0 = <&spi_0_pins>;
  24. pinctrl-names = "default";
  25. status = "okay";
  26. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
  27. <&tlmm 59 GPIO_ACTIVE_HIGH>,
  28. <&tlmm 1 GPIO_ACTIVE_HIGH>;
  29. flash@0 {
  30. compatible = "jedec,spi-nor";
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. reg = <0>;
  34. spi-max-frequency = <24000000>;
  35. partitions {
  36. compatible = "fixed-partitions";
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. partition@0 {
  40. label = "0:SBL1";
  41. reg = <0x0 0x40000>;
  42. read-only;
  43. };
  44. partition@40000 {
  45. label = "0:MIBIB";
  46. reg = <0x40000 0x20000>;
  47. read-only;
  48. };
  49. partition@60000 {
  50. label = "0:QSEE";
  51. reg = <0x60000 0x60000>;
  52. read-only;
  53. };
  54. partition@c0000 {
  55. label = "0:CDT";
  56. reg = <0xc0000 0x10000>;
  57. read-only;
  58. };
  59. partition@d0000 {
  60. label = "0:DDRPARAMS";
  61. reg = <0xd0000 0x10000>;
  62. read-only;
  63. };
  64. partition@e0000 {
  65. label = "0:APPSBLENV";
  66. reg = <0xe0000 0x10000>;
  67. read-only;
  68. };
  69. partition@f0000 {
  70. label = "0:APPSBL";
  71. reg = <0xf0000 0xc0000>;
  72. read-only;
  73. };
  74. partition@1b0000 {
  75. label = "0:reserved1";
  76. reg = <0x1b0000 0x50000>;
  77. read-only;
  78. };
  79. };
  80. };
  81. spi-nand@1 { /* flash@1 ? */
  82. compatible = "spi-nand";
  83. reg = <1>;
  84. spi-max-frequency = <24000000>;
  85. partitions {
  86. compatible = "fixed-partitions";
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. partition@0 {
  90. label = "fota-flag";
  91. reg = <0x0 0x140000>;
  92. read-only;
  93. };
  94. partition@140000 {
  95. label = "ART";
  96. reg = <0x140000 0x140000>;
  97. read-only;
  98. nvmem-layout {
  99. compatible = "fixed-layout";
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. precal_art_1000: precal@1000 {
  103. reg = <0x1000 0x2f20>;
  104. };
  105. precal_art_5000: precal@5000 {
  106. reg = <0x5000 0x2f20>;
  107. };
  108. };
  109. };
  110. partition@280000 {
  111. label = "mac";
  112. reg = <0x280000 0x140000>;
  113. read-only;
  114. nvmem-layout {
  115. compatible = "fixed-layout";
  116. #address-cells = <1>;
  117. #size-cells = <1>;
  118. macaddr_mac_0: macaddr@0 {
  119. compatible = "mac-base";
  120. reg = <0x0 0x6>;
  121. #nvmem-cell-cells = <1>;
  122. };
  123. };
  124. };
  125. partition@3c0000 {
  126. label = "cfg-param";
  127. reg = <0x3c0000 0x600000>;
  128. read-only;
  129. };
  130. partition@9c0000 {
  131. label = "oops";
  132. reg = <0x9c0000 0x140000>;
  133. };
  134. partition@b00000 {
  135. label = "web";
  136. reg = <0xb00000 0x800000>;
  137. };
  138. partition@1300000 {
  139. label = "rootfs";
  140. reg = <0x1300000 0x2200000>;
  141. };
  142. partition@3500000 {
  143. label = "data";
  144. reg = <0x3500000 0x1900000>;
  145. };
  146. partition@4e00000 {
  147. label = "fota";
  148. reg = <0x4e00000 0x3200000>;
  149. };
  150. };
  151. };
  152. zigbee@2 {
  153. #address-cells = <1>;
  154. #size-cells = <0>;
  155. compatible = "silabs,em3581";
  156. reg = <2>;
  157. spi-max-frequency = <12000000>;
  158. };
  159. };
  160. &tlmm {
  161. serial_pins: serial_pinmux {
  162. mux {
  163. pins = "gpio60", "gpio61";
  164. function = "blsp_uart0";
  165. bias-disable;
  166. };
  167. };
  168. spi_0_pins: spi_0_pinmux {
  169. pinmux {
  170. function = "blsp_spi0";
  171. pins = "gpio55", "gpio56", "gpio57";
  172. drive-strength = <12>;
  173. bias-disable;
  174. };
  175. pinmux_cs {
  176. function = "gpio";
  177. pins = "gpio54", "gpio59", "gpio1";
  178. drive-strength = <2>;
  179. bias-disable;
  180. output-high;
  181. };
  182. };
  183. };
  184. &wifi0 {
  185. qcom,ath10k-calibration-variant = "zte,mf287";
  186. };
  187. &wifi1{
  188. qcom,ath10k-calibration-variant = "zte,mf287";
  189. };