qcom-ipq4018-mf287pro.dts 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2022, Pawel Dembicki <[email protected]>.
  3. // Copyright (c) 2022, Giammarco Marzano <[email protected]>.
  4. // Copyright (c) 2023, Andreas Böhler <[email protected]>
  5. #include "qcom-ipq4018-mf287_common.dtsi"
  6. / {
  7. model = "ZTE MF287Pro";
  8. compatible = "zte,mf287pro";
  9. regulator-usb-vbus {
  10. compatible = "regulator-fixed";
  11. regulator-name = "USB_VBUS";
  12. regulator-min-microvolt = <5000000>;
  13. regulator-max-microvolt = <5000000>;
  14. regulator-always-on;
  15. regulator-boot-on;
  16. gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
  17. };
  18. };
  19. &gpio_modem_reset {
  20. gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
  21. };
  22. &key_reset {
  23. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  24. };
  25. &key_wps {
  26. gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
  27. };
  28. &led_status {
  29. gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
  30. };
  31. &mdio {
  32. status = "okay";
  33. pinctrl-0 = <&mdio_pins>;
  34. pinctrl-names = "default";
  35. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  36. reset-delay-us = <2000>;
  37. };
  38. &blsp1_spi1 {
  39. pinctrl-0 = <&spi_0_pins>;
  40. pinctrl-names = "default";
  41. status = "okay";
  42. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
  43. <&tlmm 54 GPIO_ACTIVE_HIGH>;
  44. flash@0 {
  45. compatible = "jedec,spi-nor";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. reg = <0>;
  49. spi-max-frequency = <24000000>;
  50. partitions {
  51. compatible = "fixed-partitions";
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. partition@0 {
  55. label = "0:SBL1";
  56. reg = <0x0 0x40000>;
  57. read-only;
  58. };
  59. partition@40000 {
  60. label = "0:MIBIB";
  61. reg = <0x40000 0x20000>;
  62. read-only;
  63. };
  64. partition@60000 {
  65. label = "0:QSEE";
  66. reg = <0x60000 0x60000>;
  67. read-only;
  68. };
  69. partition@c0000 {
  70. label = "0:CDT";
  71. reg = <0xc0000 0x10000>;
  72. read-only;
  73. };
  74. partition@d0000 {
  75. label = "0:DDRPARAMS";
  76. reg = <0xd0000 0x10000>;
  77. read-only;
  78. };
  79. partition@e0000 {
  80. label = "0:APPSBLENV";
  81. reg = <0xe0000 0x10000>;
  82. read-only;
  83. };
  84. partition@f0000 {
  85. label = "0:APPSBL";
  86. reg = <0xf0000 0xc0000>;
  87. read-only;
  88. };
  89. partition@1b0000 {
  90. label = "0:reserved1";
  91. reg = <0x1b0000 0x50000>;
  92. read-only;
  93. };
  94. };
  95. };
  96. spi-nand@1 { /* flash@1 ? */
  97. compatible = "spi-nand";
  98. reg = <1>;
  99. spi-max-frequency = <24000000>;
  100. partitions {
  101. compatible = "fixed-partitions";
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. partition@0 {
  105. label = "fota-flag";
  106. reg = <0x0 0xa0000>;
  107. read-only;
  108. };
  109. partition@a0000 {
  110. label = "ART";
  111. reg = <0xa0000 0x80000>;
  112. read-only;
  113. nvmem-layout {
  114. compatible = "fixed-layout";
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. precal_art_1000: precal@1000 {
  118. reg = <0x1000 0x2f20>;
  119. };
  120. precal_art_5000: precal@5000 {
  121. reg = <0x5000 0x2f20>;
  122. };
  123. };
  124. };
  125. partition@120000 {
  126. label = "mac";
  127. reg = <0x120000 0x80000>;
  128. read-only;
  129. nvmem-layout {
  130. compatible = "fixed-layout";
  131. #address-cells = <1>;
  132. #size-cells = <1>;
  133. macaddr_mac_0: macaddr@0 {
  134. compatible = "mac-base";
  135. reg = <0x0 0x6>;
  136. #nvmem-cell-cells = <1>;
  137. };
  138. };
  139. };
  140. partition@1a0000 {
  141. label = "reserved2";
  142. reg = <0x1a0000 0xc0000>;
  143. };
  144. partition@260000 {
  145. label = "cfg-param";
  146. reg = <0x260000 0x400000>;
  147. read-only;
  148. };
  149. partition@660000 {
  150. label = "log";
  151. reg = <0x660000 0x400000>;
  152. };
  153. partition@a60000 {
  154. label = "oops";
  155. reg = <0xa60000 0xa0000>;
  156. };
  157. partition@b00000 {
  158. label = "reserved3";
  159. reg = <0xb00000 0x500000>;
  160. };
  161. partition@1000000 {
  162. label = "web";
  163. reg = <0x1000000 0x800000>;
  164. };
  165. partition@1800000 {
  166. label = "rootfs";
  167. reg = <0x1800000 0x1d00000>;
  168. };
  169. partition@3500000 {
  170. label = "data";
  171. reg = <0x3500000 0x1900000>;
  172. };
  173. partition@4e00000 {
  174. label = "fota";
  175. reg = <0x4e00000 0x3200000>;
  176. };
  177. };
  178. };
  179. };
  180. &tlmm {
  181. i2c_0_pins: i2c_0_pinmux {
  182. mux {
  183. pins = "gpio20", "gpio21";
  184. function = "blsp_i2c0";
  185. bias-disable;
  186. };
  187. };
  188. mdio_pins: mdio_pinmux {
  189. mux_1 {
  190. pins = "gpio6";
  191. function = "mdio";
  192. bias-pull-up;
  193. };
  194. mux_2 {
  195. pins = "gpio7";
  196. function = "mdc";
  197. bias-pull-up;
  198. };
  199. };
  200. serial_pins: serial_pinmux {
  201. mux {
  202. pins = "gpio16", "gpio17";
  203. function = "blsp_uart0";
  204. bias-disable;
  205. };
  206. };
  207. spi_0_pins: spi_0_pinmux {
  208. pinmux {
  209. function = "blsp_spi0";
  210. pins = "gpio12", "gpio13", "gpio14", "gpio15";
  211. drive-strength = <12>;
  212. bias-disable;
  213. };
  214. pinmux_cs {
  215. function = "gpio";
  216. pins = "gpio12", "gpio54";
  217. drive-strength = <2>;
  218. bias-disable;
  219. output-high;
  220. };
  221. };
  222. };
  223. /* The MF287Plus and MF287Pro share the same board data file */
  224. &wifi0 {
  225. qcom,ath10k-calibration-variant = "zte,mf287plus";
  226. };
  227. /* The MF287Plus and MF287Pro share the same board data file */
  228. &wifi1{
  229. qcom,ath10k-calibration-variant = "zte,mf287plus";
  230. };