qcom-ipq4018-wrtq-329acn.dts 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "Luma Home WRTQ-329ACN";
  8. compatible = "luma,wrtq-329acn";
  9. i2c-gpio {
  10. compatible = "i2c-gpio";
  11. sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  12. scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. /* No driver exists */
  16. led_ring@48 {
  17. compatible = "ti,msp430";
  18. reg = <0x48>;
  19. };
  20. eeprom@50 {
  21. compatible = "atmel,24c16";
  22. reg = <0x50>;
  23. pagesize = <16>;
  24. read-only;
  25. };
  26. };
  27. keys {
  28. compatible = "gpio-keys";
  29. reset {
  30. label = "reset";
  31. gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_RESTART>;
  33. };
  34. };
  35. soc {
  36. rng@22000 {
  37. status = "okay";
  38. };
  39. tcsr@1949000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1949000 0x100>;
  42. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  43. };
  44. tcsr@194b000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x194b000 0x100>;
  47. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  48. };
  49. ess_tcsr@1953000 {
  50. compatible = "qcom,tcsr";
  51. reg = <0x1953000 0x1000>;
  52. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  53. };
  54. tcsr@1957000 {
  55. compatible = "qcom,tcsr";
  56. reg = <0x1957000 0x100>;
  57. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  58. };
  59. usb2@60f8800 {
  60. status = "okay";
  61. };
  62. usb3@8af8800 {
  63. status = "okay";
  64. };
  65. crypto@8e3a000 {
  66. status = "okay";
  67. };
  68. watchdog@b017000 {
  69. status = "okay";
  70. };
  71. };
  72. };
  73. &blsp_dma {
  74. status = "okay";
  75. };
  76. &blsp1_spi1 {
  77. status = "okay";
  78. cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
  79. <&tlmm 59 GPIO_ACTIVE_HIGH>;
  80. pinctrl-0 = <&spi0_pins>;
  81. pinctrl-names = "default";
  82. flash@0 {
  83. compatible = "jedec,spi-nor";
  84. reg = <0>;
  85. spi-max-frequency = <24000000>;
  86. partitions {
  87. compatible = "fixed-partitions";
  88. #address-cells = <1>;
  89. #size-cells = <1>;
  90. partition@0 {
  91. label = "0:SBL1";
  92. reg = <0x000000 0x040000>;
  93. read-only;
  94. };
  95. partition@40000 {
  96. label = "0:MIBIB";
  97. reg = <0x040000 0x020000>;
  98. read-only;
  99. };
  100. partition@60000 {
  101. label = "0:QSEE";
  102. reg = <0x060000 0x060000>;
  103. read-only;
  104. };
  105. partition@c0000 {
  106. label = "0:CDT";
  107. reg = <0x0c0000 0x010000>;
  108. read-only;
  109. };
  110. partition@d0000 {
  111. label = "0:DDRPARAMS";
  112. reg = <0x0d0000 0x010000>;
  113. read-only;
  114. };
  115. partition@e0000 {
  116. label = "0:APPSBLENV";
  117. reg = <0x0e0000 0x010000>;
  118. };
  119. partition@f0000 {
  120. label = "0:APPSBL";
  121. reg = <0x0f0000 0x080000>;
  122. read-only;
  123. };
  124. partition@170000 {
  125. label = "0:ART";
  126. reg = <0x170000 0x010000>;
  127. read-only;
  128. nvmem-layout {
  129. compatible = "fixed-layout";
  130. #address-cells = <1>;
  131. #size-cells = <1>;
  132. macaddr_art_0: macaddr@0{
  133. reg = <0x0000 0x0006>;
  134. };
  135. macaddr_art_6: macaddr@6{
  136. reg = <0x0006 0x0006>;
  137. };
  138. precal_art_1000: precal@1000 {
  139. reg = <0x1000 0x2f20>;
  140. };
  141. precal_art_5000: precal@5000 {
  142. reg = <0x5000 0x2f20>;
  143. };
  144. };
  145. };
  146. };
  147. };
  148. flash@1 {
  149. status = "okay";
  150. compatible = "spi-nand";
  151. reg = <1>;
  152. spi-max-frequency = <24000000>;
  153. partitions {
  154. compatible = "fixed-partitions";
  155. #address-cells = <1>;
  156. #size-cells = <1>;
  157. partition@0 {
  158. label = "ubi";
  159. reg = <0x0000000 0x8000000>;
  160. };
  161. };
  162. };
  163. };
  164. &blsp1_uart1 {
  165. status = "okay";
  166. pinctrl-0 = <&serial0_pins>;
  167. pinctrl-names = "default";
  168. };
  169. &cryptobam {
  170. status = "okay";
  171. };
  172. &gmac {
  173. status = "okay";
  174. };
  175. &ethphy0 {
  176. status = "disabled";
  177. };
  178. &ethphy1 {
  179. status = "disabled";
  180. };
  181. &ethphy3 {
  182. status = "disabled";
  183. };
  184. &mdio {
  185. status = "okay";
  186. };
  187. &switch {
  188. status = "okay";
  189. };
  190. &swport3 {
  191. status = "okay";
  192. label = "lan";
  193. nvmem-cell-names = "mac-address";
  194. nvmem-cells = <&macaddr_art_6>;
  195. };
  196. &swport5 {
  197. status = "okay";
  198. nvmem-cell-names = "mac-address";
  199. nvmem-cells = <&macaddr_art_0>;
  200. };
  201. &tlmm {
  202. serial0_pins: serial0_pinmux {
  203. mux {
  204. function = "blsp_uart0";
  205. pins = "gpio60", "gpio61";
  206. bias-disable;
  207. };
  208. };
  209. spi0_pins: spi0_pinmux {
  210. mux {
  211. function = "blsp_spi0";
  212. pins = "gpio55", "gpio56", "gpio57";
  213. bias-disable;
  214. drive-strength = <12>;
  215. };
  216. mux_cs {
  217. function = "gpio";
  218. pins = "gpio54", "gpio59";
  219. bias-disable;
  220. drive-strength = <2>;
  221. output-high;
  222. };
  223. };
  224. };
  225. &usb2_hs_phy {
  226. status = "okay";
  227. };
  228. &usb3_hs_phy {
  229. status = "okay";
  230. };
  231. &usb3_ss_phy {
  232. status = "okay";
  233. };
  234. &wifi0 {
  235. status = "okay";
  236. nvmem-cell-names = "pre-calibration";
  237. nvmem-cells = <&precal_art_1000>;
  238. qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
  239. };
  240. &wifi1 {
  241. status = "okay";
  242. nvmem-cell-names = "pre-calibration";
  243. nvmem-cells = <&precal_art_5000>;
  244. qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
  245. };