qcom-ipq4019-gl-b2200.dts 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include <dt-bindings/soc/qcom,tcsr.h>
  7. / {
  8. model = "GL.iNet GL-B2200";
  9. compatible = "glinet,gl-b2200", "qcom,ipq4019";
  10. memory {
  11. device_type = "memory";
  12. reg = <0x80000000 0x10000000>;
  13. };
  14. chosen {
  15. bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
  16. };
  17. aliases {
  18. ethernet1 = &swport4;
  19. };
  20. soc {
  21. rng@22000 {
  22. status = "okay";
  23. };
  24. mdio@90000 {
  25. status = "okay";
  26. };
  27. tcsr@1949000 {
  28. compatible = "qcom,tcsr";
  29. reg = <0x1949000 0x100>;
  30. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  31. };
  32. tcsr@194b000 {
  33. /* select hostmode */
  34. compatible = "qcom,tcsr";
  35. reg = <0x194b000 0x100>;
  36. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  37. status = "okay";
  38. };
  39. ess_tcsr@1953000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1953000 0x1000>;
  42. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  43. };
  44. tcsr@1957000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x1957000 0x100>;
  47. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  48. };
  49. crypto@8e3a000 {
  50. status = "okay";
  51. };
  52. };
  53. keys {
  54. compatible = "gpio-keys";
  55. wps {
  56. label = "wps";
  57. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  58. linux,code = <KEY_WPS_BUTTON>;
  59. linux,input-type = <1>;
  60. };
  61. reset {
  62. label = "reset";
  63. gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
  64. linux,code = <KEY_RESTART>;
  65. linux,input-type = <1>;
  66. };
  67. };
  68. leds {
  69. compatible = "gpio-leds";
  70. power_blue {
  71. function = LED_FUNCTION_POWER;
  72. color = <LED_COLOR_ID_BLUE>;
  73. gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
  74. default-state = "on";
  75. };
  76. internet_blue {
  77. label = "blue:internet";
  78. gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
  79. };
  80. power_white {
  81. function = LED_FUNCTION_POWER;
  82. color = <LED_COLOR_ID_WHITE>;
  83. gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
  84. };
  85. internet_white {
  86. label = "white:internet";
  87. gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
  88. };
  89. };
  90. };
  91. &vqmmc {
  92. status = "okay";
  93. };
  94. &sdhci {
  95. status = "okay";
  96. pinctrl-0 = <&sd_pins>;
  97. pinctrl-names = "default";
  98. cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
  99. vqmmc-supply = <&vqmmc>;
  100. };
  101. &blsp_dma {
  102. status = "okay";
  103. };
  104. &cryptobam {
  105. status = "okay";
  106. };
  107. &blsp1_spi1 {
  108. pinctrl-0 = <&spi_0_pins>;
  109. pinctrl-names = "default";
  110. status = "okay";
  111. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  112. flash@0 {
  113. compatible = "jedec,spi-nor";
  114. reg = <0>;
  115. spi-max-frequency = <24000000>;
  116. partitions {
  117. compatible = "fixed-partitions";
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. partition@0 {
  121. label = "SBL1";
  122. reg = <0x0 0x40000>;
  123. read-only;
  124. };
  125. partition@40000 {
  126. label = "MIBIB";
  127. reg = <0x40000 0x20000>;
  128. read-only;
  129. };
  130. partition@60000 {
  131. label = "QSEE";
  132. reg = <0x60000 0x60000>;
  133. read-only;
  134. };
  135. partition@c0000 {
  136. label = "CDT";
  137. reg = <0xc0000 0x10000>;
  138. read-only;
  139. };
  140. partition@d0000 {
  141. label = "DDRPARAMS";
  142. reg = <0xd0000 0x10000>;
  143. read-only;
  144. };
  145. partition@e0000 {
  146. label = "APPSBLENV";
  147. reg = <0xe0000 0x10000>;
  148. read-only;
  149. };
  150. partition@f0000 {
  151. label = "APPSBL";
  152. reg = <0xf0000 0x80000>;
  153. read-only;
  154. };
  155. partition@170000 {
  156. label = "ART";
  157. reg = <0x170000 0x10000>;
  158. read-only;
  159. nvmem-layout {
  160. compatible = "fixed-layout";
  161. #address-cells = <1>;
  162. #size-cells = <1>;
  163. precal_art_1000: precal@1000 {
  164. reg = <0x1000 0x2f20>;
  165. };
  166. precal_art_5000: precal@5000 {
  167. reg = <0x5000 0x2f20>;
  168. };
  169. precal_art_9000: precal@9000 {
  170. reg = <0x9000 0x2f20>;
  171. };
  172. };
  173. };
  174. };
  175. };
  176. };
  177. &blsp1_spi2 {
  178. pinctrl-0 = <&spi_1_pins>;
  179. pinctrl-names = "default";
  180. status = "okay";
  181. spidev1: spi@0 {
  182. compatible = "silabs,si3210";
  183. reg = <0>;
  184. spi-max-frequency = <24000000>;
  185. };
  186. };
  187. &blsp1_uart1 {
  188. pinctrl-0 = <&serial_pins>;
  189. pinctrl-names = "default";
  190. status = "okay";
  191. };
  192. &blsp1_uart2 {
  193. pinctrl-0 = <&serial_1_pins>;
  194. pinctrl-names = "default";
  195. status = "okay";
  196. };
  197. &tlmm {
  198. serial_pins: serial_pinmux {
  199. mux {
  200. pins = "gpio16", "gpio17";
  201. function = "blsp_uart0";
  202. bias-disable;
  203. };
  204. };
  205. serial_1_pins: serial1_pinmux {
  206. mux {
  207. pins = "gpio8", "gpio9",
  208. "gpio10", "gpio11";
  209. function = "blsp_uart1";
  210. bias-disable;
  211. };
  212. };
  213. spi_0_pins: spi_0_pinmux {
  214. pinmux {
  215. function = "blsp_spi0";
  216. pins = "gpio13", "gpio14", "gpio15";
  217. };
  218. pinmux_cs {
  219. function = "gpio";
  220. pins = "gpio12";
  221. };
  222. pinconf {
  223. pins = "gpio13", "gpio14", "gpio15";
  224. drive-strength = <12>;
  225. bias-disable;
  226. };
  227. pinconf_cs {
  228. pins = "gpio12";
  229. drive-strength = <2>;
  230. bias-disable;
  231. output-high;
  232. };
  233. };
  234. spi_1_pins: spi_1_pinmux {
  235. mux {
  236. pins = "gpio44", "gpio46", "gpio47";
  237. function = "blsp_spi1";
  238. bias-disable;
  239. };
  240. cs {
  241. pins = "gpio45";
  242. function = "gpio";
  243. bias-pull-up;
  244. };
  245. reset {
  246. pins = "gpio43";
  247. function = "gpio";
  248. output-high;
  249. };
  250. mux_2 {
  251. pins = "gpio35";
  252. function = "gpio";
  253. output-high;
  254. };
  255. host_int {
  256. pins = "gpio2";
  257. function = "gpio";
  258. input;
  259. };
  260. wake {
  261. pins = "gpio48";
  262. function = "gpio";
  263. output-high;
  264. };
  265. };
  266. sd_pins: sd_pins {
  267. pinmux {
  268. function = "sdio";
  269. pins = "gpio23", "gpio24", "gpio25", "gpio26",
  270. "gpio29", "gpio30", "gpio31", "gpio32";
  271. drive-strength = <10>;
  272. };
  273. pinmux_sd_clk {
  274. function = "sdio";
  275. pins = "gpio27";
  276. drive-strength = <16>;
  277. };
  278. pinmux_sd7 {
  279. function = "sdio";
  280. pins = "gpio28";
  281. drive-strength = <10>;
  282. bias-disable;
  283. };
  284. };
  285. };
  286. &pcie0 {
  287. status = "okay";
  288. perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
  289. wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
  290. bridge@0,0 {
  291. reg = <0x00000000 0 0 0 0>;
  292. #address-cells = <3>;
  293. #size-cells = <2>;
  294. ranges;
  295. wifi2: wifi@1,0 {
  296. status = "okay";
  297. /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
  298. compatible = "qcom,ath10k";
  299. reg = <0x00010000 0 0 0 0>;
  300. nvmem-cell-names = "pre-calibration";
  301. nvmem-cells = <&precal_art_9000>;
  302. qcom,ath10k-calibration-variant = "GL-B2200";
  303. ieee80211-freq-limit = <5450000 5900000>;
  304. };
  305. };
  306. };
  307. &gmac {
  308. status = "okay";
  309. };
  310. &switch {
  311. status = "okay";
  312. };
  313. &swport4 {
  314. status = "okay";
  315. label = "wan";
  316. };
  317. &swport5 {
  318. status = "okay";
  319. label = "lan";
  320. };
  321. &wifi0 {
  322. status = "okay";
  323. nvmem-cell-names = "pre-calibration";
  324. nvmem-cells = <&precal_art_1000>;
  325. qcom,ath10k-calibration-variant = "GL-B2200";
  326. };
  327. &wifi1 {
  328. status = "okay";
  329. nvmem-cell-names = "pre-calibration";
  330. nvmem-cells = <&precal_art_5000>;
  331. qcom,ath10k-calibration-variant = "GL-B2200";
  332. ieee80211-freq-limit = <5100000 5400000>;
  333. };