qcom-ipq4019-habanero-dvk.dts 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /* Copyright (c) 2019, Robert Marko <[email protected]> */
  3. #include "qcom-ipq4019.dtsi"
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/input/input.h>
  6. #include <dt-bindings/leds/common.h>
  7. #include <dt-bindings/soc/qcom,tcsr.h>
  8. / {
  9. model = "8devices Habanero DVK";
  10. compatible = "8dev,habanero-dvk";
  11. aliases {
  12. led-boot = &led_status;
  13. led-failsafe = &led_status;
  14. led-running = &led_status;
  15. led-upgrade = &led_upgrade;
  16. ethernet1 = &swport5;
  17. };
  18. soc {
  19. rng@22000 {
  20. status = "okay";
  21. };
  22. mdio@90000 {
  23. status = "okay";
  24. pinctrl-0 = <&mdio_pins>;
  25. pinctrl-names = "default";
  26. };
  27. counter@4a1000 {
  28. compatible = "qcom,qca-gcnt";
  29. reg = <0x4a1000 0x4>;
  30. };
  31. tcsr@1949000 {
  32. compatible = "qcom,tcsr";
  33. reg = <0x1949000 0x100>;
  34. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  35. };
  36. tcsr@194b000 {
  37. status = "okay";
  38. compatible = "qcom,tcsr";
  39. reg = <0x194b000 0x100>;
  40. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  41. };
  42. ess_tcsr@1953000 {
  43. compatible = "qcom,tcsr";
  44. reg = <0x1953000 0x1000>;
  45. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  46. };
  47. tcsr@1957000 {
  48. compatible = "qcom,tcsr";
  49. reg = <0x1957000 0x100>;
  50. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  51. };
  52. usb2: usb2@60f8800 {
  53. status = "okay";
  54. };
  55. usb3: usb3@8af8800 {
  56. status = "okay";
  57. };
  58. crypto@8e3a000 {
  59. status = "okay";
  60. };
  61. watchdog@b017000 {
  62. status = "okay";
  63. };
  64. };
  65. keys {
  66. compatible = "gpio-keys";
  67. reset {
  68. label = "reset";
  69. gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
  70. linux,code = <KEY_RESTART>;
  71. };
  72. };
  73. leds {
  74. compatible = "gpio-leds";
  75. led_status: status {
  76. function = LED_FUNCTION_STATUS;
  77. color = <LED_COLOR_ID_GREEN>;
  78. gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
  79. panic-indicator;
  80. };
  81. led_upgrade: upgrade {
  82. label = "green:upgrade";
  83. gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  84. };
  85. wlan2g {
  86. label = "green:wlan2g";
  87. gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
  88. linux,default-trigger = "phy0tpt";
  89. };
  90. wlan5g {
  91. label = "green:wlan5g";
  92. gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
  93. linux,default-trigger = "phy1tpt";
  94. };
  95. };
  96. };
  97. &vqmmc {
  98. status = "okay";
  99. };
  100. &sdhci {
  101. status = "okay";
  102. pinctrl-0 = <&sd_pins>;
  103. pinctrl-names = "default";
  104. cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
  105. vqmmc-supply = <&vqmmc>;
  106. };
  107. &qpic_bam {
  108. status = "okay";
  109. };
  110. &tlmm {
  111. mdio_pins: mdio_pinmux {
  112. mux_1 {
  113. pins = "gpio6";
  114. function = "mdio";
  115. bias-pull-up;
  116. };
  117. mux_2 {
  118. pins = "gpio7";
  119. function = "mdc";
  120. bias-pull-up;
  121. };
  122. };
  123. serial_pins: serial_pinmux {
  124. mux {
  125. pins = "gpio16", "gpio17";
  126. function = "blsp_uart0";
  127. bias-disable;
  128. };
  129. };
  130. spi_0_pins: spi_0_pinmux {
  131. pinmux {
  132. function = "blsp_spi0";
  133. pins = "gpio13", "gpio14", "gpio15";
  134. drive-strength = <12>;
  135. bias-disable;
  136. };
  137. pinmux_cs {
  138. function = "gpio";
  139. pins = "gpio12";
  140. drive-strength = <2>;
  141. bias-disable;
  142. output-high;
  143. };
  144. };
  145. nand_pins: nand_pins {
  146. pullups {
  147. pins = "gpio52", "gpio53", "gpio58", "gpio59";
  148. function = "qpic";
  149. bias-pull-up;
  150. };
  151. pulldowns {
  152. pins = "gpio54", "gpio55", "gpio56", "gpio57",
  153. "gpio60", "gpio62", "gpio63", "gpio64",
  154. "gpio65", "gpio66", "gpio67", "gpio68",
  155. "gpio69";
  156. function = "qpic";
  157. bias-pull-down;
  158. };
  159. };
  160. sd_pins: sd_pins {
  161. pinmux {
  162. function = "sdio";
  163. pins = "gpio23", "gpio24", "gpio25", "gpio26",
  164. "gpio28", "gpio29", "gpio30", "gpio31";
  165. drive-strength = <10>;
  166. };
  167. pinmux_sd_clk {
  168. function = "sdio";
  169. pins = "gpio27";
  170. drive-strength = <16>;
  171. };
  172. pinmux_sd7 {
  173. function = "sdio";
  174. pins = "gpio32";
  175. drive-strength = <10>;
  176. bias-disable;
  177. };
  178. };
  179. };
  180. &blsp_dma {
  181. status = "okay";
  182. };
  183. &blsp1_spi1 {
  184. status = "okay";
  185. pinctrl-0 = <&spi_0_pins>;
  186. pinctrl-names = "default";
  187. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  188. flash@0 {
  189. compatible = "jedec,spi-nor";
  190. spi-max-frequency = <24000000>;
  191. reg = <0>;
  192. partitions {
  193. compatible = "fixed-partitions";
  194. #address-cells = <1>;
  195. #size-cells = <1>;
  196. partition@0 {
  197. label = "SBL1";
  198. reg = <0x00000000 0x00040000>;
  199. read-only;
  200. };
  201. partition@40000 {
  202. label = "MIBIB";
  203. reg = <0x00040000 0x00020000>;
  204. read-only;
  205. };
  206. partition@60000 {
  207. label = "QSEE";
  208. reg = <0x00060000 0x00060000>;
  209. read-only;
  210. };
  211. partition@c0000 {
  212. label = "CDT";
  213. reg = <0x000c0000 0x00010000>;
  214. read-only;
  215. };
  216. partition@d0000 {
  217. label = "DDRPARAMS";
  218. reg = <0x000d0000 0x00010000>;
  219. read-only;
  220. };
  221. partition@e0000 {
  222. label = "APPSBLENV"; /* uboot env */
  223. reg = <0x000e0000 0x00010000>;
  224. read-only;
  225. };
  226. partition@f0000 {
  227. label = "APPSBL"; /* uboot */
  228. reg = <0x000f0000 0x00080000>;
  229. read-only;
  230. };
  231. partition@170000 {
  232. label = "ART";
  233. reg = <0x00170000 0x00010000>;
  234. read-only;
  235. nvmem-layout {
  236. compatible = "fixed-layout";
  237. #address-cells = <1>;
  238. #size-cells = <1>;
  239. precal_art_1000: precal@1000 {
  240. reg = <0x1000 0x2f20>;
  241. };
  242. precal_art_5000: precal@5000 {
  243. reg = <0x5000 0x2f20>;
  244. };
  245. };
  246. };
  247. partition@180000 {
  248. label = "cfg";
  249. reg = <0x00180000 0x00040000>;
  250. };
  251. partition@1c0000 {
  252. label = "firmware";
  253. compatible = "denx,fit";
  254. reg = <0x001c0000 0x01e40000>;
  255. };
  256. };
  257. };
  258. };
  259. /* Some DVK boards ship without NAND */
  260. &nand {
  261. status = "okay";
  262. pinctrl-0 = <&nand_pins>;
  263. pinctrl-names = "default";
  264. };
  265. &blsp1_uart1 {
  266. status = "okay";
  267. pinctrl-0 = <&serial_pins>;
  268. pinctrl-names = "default";
  269. };
  270. &cryptobam {
  271. status = "okay";
  272. };
  273. &pcie0 {
  274. status = "okay";
  275. perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
  276. wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
  277. /* Free slot for use */
  278. bridge@0,0 {
  279. reg = <0x00000000 0 0 0 0>;
  280. #address-cells = <3>;
  281. #size-cells = <2>;
  282. ranges;
  283. };
  284. };
  285. &gmac {
  286. status = "okay";
  287. };
  288. &switch {
  289. status = "okay";
  290. };
  291. &swport1 {
  292. status = "okay";
  293. };
  294. &swport2 {
  295. status = "okay";
  296. };
  297. &swport3 {
  298. status = "okay";
  299. };
  300. &swport4 {
  301. status = "okay";
  302. };
  303. &swport5 {
  304. status = "okay";
  305. };
  306. &wifi0 {
  307. status = "okay";
  308. nvmem-cell-names = "pre-calibration";
  309. nvmem-cells = <&precal_art_1000>;
  310. qcom,ath10k-calibration-variant = "8devices-Habanero";
  311. };
  312. &wifi1 {
  313. status = "okay";
  314. nvmem-cell-names = "pre-calibration";
  315. nvmem-cells = <&precal_art_5000>;
  316. qcom,ath10k-calibration-variant = "8devices-Habanero";
  317. };
  318. &usb3_ss_phy {
  319. status = "okay";
  320. };
  321. &usb3_hs_phy {
  322. status = "okay";
  323. };
  324. &usb2_hs_phy {
  325. status = "okay";
  326. };