qcom-ipq4019-lbr20.dts 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/leds/common.h>
  7. / {
  8. model = "Netgear LBR20";
  9. compatible = "netgear,lbr20";
  10. chosen {
  11. bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
  12. };
  13. aliases {
  14. led-boot = &led_backlight_white;
  15. led-failsafe = &led_status_green;
  16. led-running = &led_status_green;
  17. led-upgrade = &led_status_red;
  18. label-mac-device = &gmac;
  19. };
  20. keys {
  21. compatible = "gpio-keys";
  22. reset {
  23. label = "reset";
  24. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  25. linux,code = <KEY_RESTART>;
  26. };
  27. wps {
  28. label = "wps";
  29. gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
  30. linux,code = <KEY_WPS_BUTTON>;
  31. };
  32. };
  33. leds {
  34. compatible = "gpio-leds";
  35. led_status_green: led-status-green {
  36. function = LED_FUNCTION_STATUS;
  37. color = <LED_COLOR_ID_GREEN>;
  38. gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
  39. default-state = "keep";
  40. };
  41. led_status_red: led-status-red {
  42. function = LED_FUNCTION_STATUS;
  43. color = <LED_COLOR_ID_RED>;
  44. gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
  45. };
  46. };
  47. gpio_export {
  48. compatible = "gpio-export";
  49. #size-cells = <0>;
  50. lte_rst {
  51. gpio-export,name = "lte_rst";
  52. gpio-export,output = <1>;
  53. gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
  54. };
  55. lte_pwrkey {
  56. gpio-export,name = "lte_pwrkey";
  57. gpio-export,output = <1>;
  58. gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
  59. };
  60. lte_usb_boot {
  61. gpio-export,name = "lte_usb_boot";
  62. gpio-export,output = <0>;
  63. gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
  64. };
  65. lte_pwm {
  66. gpio-export,name = "lte_pwm";
  67. gpio-export,output = <1>;
  68. gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
  69. };
  70. };
  71. soc {
  72. tcsr@1949000 {
  73. compatible = "qcom,tcsr";
  74. reg = <0x1949000 0x100>;
  75. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  76. };
  77. tcsr@194b000 {
  78. status = "okay";
  79. compatible = "qcom,tcsr";
  80. reg = <0x194b000 0x100>;
  81. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  82. };
  83. ess_tcsr@1953000 {
  84. compatible = "qcom,tcsr";
  85. reg = <0x1953000 0x1000>;
  86. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  87. };
  88. tcsr@1957000 {
  89. compatible = "qcom,tcsr";
  90. reg = <0x1957000 0x100>;
  91. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  92. };
  93. };
  94. };
  95. &prng {
  96. status = "okay";
  97. };
  98. &mdio {
  99. status = "okay";
  100. pinctrl-0 = <&mdio_pins>;
  101. pinctrl-names = "default";
  102. };
  103. &crypto {
  104. status = "okay";
  105. };
  106. &watchdog {
  107. status = "okay";
  108. };
  109. &usb2_hs_phy {
  110. status = "okay";
  111. };
  112. &usb2 {
  113. status = "okay";
  114. };
  115. &usb3_ss_phy {
  116. status = "okay";
  117. };
  118. &usb3_hs_phy {
  119. status = "okay";
  120. };
  121. &usb3 {
  122. status = "okay";
  123. };
  124. &blsp_dma {
  125. status = "okay";
  126. };
  127. &qpic_bam {
  128. status = "okay";
  129. };
  130. &tlmm {
  131. mdio_pins: mdio-pinmux {
  132. mux_mdio {
  133. pins = "gpio6";
  134. function = "mdio";
  135. bias-pull-up;
  136. };
  137. mux_mdc {
  138. pins = "gpio7";
  139. function = "mdc";
  140. bias-pull-up;
  141. };
  142. };
  143. serial_pins: serial-pinmux {
  144. function = "blsp_uart0";
  145. pins = "gpio16", "gpio17";
  146. bias-disable;
  147. };
  148. nand_pins: nand-pins {
  149. pullups {
  150. pins = "gpio52", "gpio53", "gpio58", "gpio59";
  151. function = "qpic";
  152. bias-pull-up;
  153. };
  154. pulldowns {
  155. pins = "gpio54", "gpio55", "gpio56",
  156. "gpio57", "gpio60", "gpio61",
  157. "gpio62", "gpio63", "gpio64",
  158. "gpio65", "gpio66", "gpio67",
  159. "gpio68", "gpio69";
  160. function = "qpic";
  161. bias-pull-down;
  162. };
  163. };
  164. };
  165. &nand {
  166. pinctrl-0 = <&nand_pins>;
  167. pinctrl-names = "default";
  168. status = "okay";
  169. nand@0 {
  170. partitions {
  171. compatible = "fixed-partitions";
  172. #address-cells = <1>;
  173. #size-cells = <1>;
  174. partition@0 {
  175. label = "0:SBL1";
  176. reg = <0x00000000 0x00100000>;
  177. read-only;
  178. };
  179. partition@100000 {
  180. label = "0:MIBIB";
  181. reg = <0x00100000 0x00100000>;
  182. read-only;
  183. };
  184. partition@200000 {
  185. label = "0:BOOTCONFIG";
  186. reg = <0x00200000 0x00100000>;
  187. read-only;
  188. };
  189. partition@300000 {
  190. label = "0:QSEE";
  191. reg = <0x00300000 0x00100000>;
  192. read-only;
  193. };
  194. partition@400000 {
  195. label = "0:QSEE_1";
  196. reg = <0x00400000 0x00100000>;
  197. read-only;
  198. };
  199. partition@500000 {
  200. label = "0:CDT";
  201. reg = <0x00500000 0x00080000>;
  202. read-only;
  203. };
  204. partition@580000 {
  205. label = "0:CDT_1";
  206. reg = <0x00580000 0x00080000>;
  207. read-only;
  208. };
  209. partition@600000 {
  210. label = "0:BOOTCONFIG1";
  211. reg = <0x00600000 0x00080000>;
  212. read-only;
  213. };
  214. partition@680000 {
  215. label = "0:APPSBLENV";
  216. reg = <0x00680000 0x00080000>;
  217. };
  218. partition@700000 {
  219. label = "0:APPSBL";
  220. reg = <0x00700000 0x00200000>;
  221. read-only;
  222. };
  223. partition@900000 {
  224. label = "0:APPSBL_1";
  225. reg = <0x00900000 0x00200000>;
  226. read-only;
  227. };
  228. partition@b00000 {
  229. label = "0:ART";
  230. reg = <0x00b00000 0x00080000>;
  231. read-only;
  232. nvmem-layout {
  233. compatible = "fixed-layout";
  234. #address-cells = <1>;
  235. #size-cells = <1>;
  236. precal_art_1000: precal@1000 {
  237. reg = <0x1000 0x2f20>;
  238. };
  239. precal_art_5000: precal@5000 {
  240. reg = <0x5000 0x2f20>;
  241. };
  242. precal_art_9000: precal@9000 {
  243. reg = <0x9000 0x2f20>;
  244. };
  245. };
  246. };
  247. partition@b80000 {
  248. label = "0:ART.bak";
  249. reg = <0x00b80000 0x00080000>;
  250. read-only;
  251. };
  252. partition@c00000 {
  253. label = "config";
  254. reg = <0x00c00000 0x00100000>;
  255. read-only;
  256. };
  257. partition@d00000 {
  258. label = "boarddata1";
  259. reg = <0x00d00000 0x00080000>;
  260. read-only;
  261. nvmem-layout {
  262. compatible = "fixed-layout";
  263. #address-cells = <1>;
  264. #size-cells = <1>;
  265. mac_address_lan: macaddr@0 {
  266. compatible = "mac-base";
  267. reg = <0x0 0x6>;
  268. #nvmem-cell-cells = <1>;
  269. };
  270. mac_address_wan: macaddr@6 {
  271. compatible = "mac-base";
  272. reg = <0x6 0x6>;
  273. #nvmem-cell-cells = <1>;
  274. };
  275. mac_address_wlan_5g: macaddr@c {
  276. compatible = "mac-base";
  277. reg = <0xc 0x6>;
  278. #nvmem-cell-cells = <1>;
  279. };
  280. mac_address_wlan_2nd5g: macaddr@12 {
  281. compatible = "mac-base";
  282. reg = <0x12 0x6>;
  283. #nvmem-cell-cells = <1>;
  284. };
  285. };
  286. };
  287. partition@d80000 {
  288. label = "boarddata2";
  289. reg = <0x00d80000 0x00040000>;
  290. read-only;
  291. };
  292. partition@dc0000 {
  293. label = "pot";
  294. reg = <0x00dc0000 0x00100000>;
  295. read-only;
  296. };
  297. partition@ec0000 {
  298. label = "boarddata1.bak";
  299. reg = <0x00ec0000 0x00080000>;
  300. read-only;
  301. };
  302. partition@f40000 {
  303. label = "boarddata2.bak";
  304. reg = <0x00f40000 0x00040000>;
  305. read-only;
  306. };
  307. partition@f80000 {
  308. label = "language";
  309. reg = <0x00f80000 0x00300000>;
  310. read-only;
  311. };
  312. partition@1280000 {
  313. label = "cert";
  314. reg = <0x01280000 0x00080000>;
  315. read-only;
  316. };
  317. partition@1300000 {
  318. label = "ntgrdata";
  319. reg = <0x01300000 0x09300000>;
  320. };
  321. partition@a600000 {
  322. label = "kernel";
  323. reg = <0x0a600000 0x00700000>;
  324. };
  325. partition@a9c0000 {
  326. label = "ubi";
  327. reg = <0x0ad00000 0x05300000>;
  328. };
  329. };
  330. };
  331. };
  332. &blsp1_i2c3 {
  333. status = "okay";
  334. led-controller {
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. compatible = "ti,tlc59108"; /* really is tlc59208f */
  338. reg = <0x27>;
  339. led_backlight_green: led-backlight-green {
  340. function = LED_FUNCTION_BACKLIGHT;
  341. color = <LED_COLOR_ID_GREEN>;
  342. reg = <0x0>;
  343. linux,default-trigger = "default-off";
  344. };
  345. led_backlight_red: led-backlight-red {
  346. function = LED_FUNCTION_BACKLIGHT;
  347. color = <LED_COLOR_ID_RED>;
  348. reg = <0x1>;
  349. linux,default-trigger = "default-off";
  350. };
  351. led_backlight_blue: led-backlight-blue {
  352. function = LED_FUNCTION_BACKLIGHT;
  353. color = <LED_COLOR_ID_BLUE>;
  354. reg = <0x2>;
  355. linux,default-trigger = "default-off";
  356. };
  357. led_backlight_white: led-backlight-white {
  358. function = LED_FUNCTION_BACKLIGHT;
  359. color = <LED_COLOR_ID_WHITE>;
  360. reg = <0x3>;
  361. linux,default-trigger = "default-off";
  362. };
  363. };
  364. };
  365. &blsp1_uart1 {
  366. status = "okay";
  367. pinctrl-0 = <&serial_pins>;
  368. pinctrl-names = "default";
  369. };
  370. &cryptobam {
  371. status = "okay";
  372. };
  373. &gmac {
  374. status = "okay";
  375. nvmem-cell-names = "mac-address";
  376. nvmem-cells = <&mac_address_lan 0>;
  377. };
  378. &switch {
  379. status = "okay";
  380. };
  381. &swport4 {
  382. status = "okay";
  383. label = "lan1";
  384. };
  385. &swport5 {
  386. status = "okay";
  387. label = "lan2";
  388. };
  389. &pcie0 {
  390. status = "okay";
  391. perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
  392. wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
  393. bridge@0,0 {
  394. reg = <0x00000000 0 0 0 0>;
  395. #address-cells = <3>;
  396. #size-cells = <2>;
  397. ranges;
  398. wifi@1,0 {
  399. compatible = "qcom,ath10k";
  400. status = "okay";
  401. reg = <0x00010000 0 0 0 0>;
  402. ieee80211-freq-limit = <5170000 5350000>;
  403. nvmem-cell-names = "pre-calibration", "mac-address";
  404. nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
  405. qcom,ath10k-calibration-variant = "Netgear-LBR20";
  406. };
  407. };
  408. };
  409. &wifi0 {
  410. status = "okay";
  411. nvmem-cell-names = "pre-calibration", "mac-address";
  412. nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
  413. qcom,ath10k-calibration-variant = "Netgear-LBR20";
  414. };
  415. &wifi1 {
  416. status = "okay";
  417. ieee80211-freq-limit = <5470000 5815000>;
  418. nvmem-cell-names = "pre-calibration", "mac-address";
  419. nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
  420. qcom,ath10k-calibration-variant = "Netgear-LBR20";
  421. };