qcom-ipq4019-mf282plus.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. // Copyright (c) 2022, Pawel Dembicki <[email protected]>.
  3. // Copyright (c) 2023, Andreas Böhler <[email protected]>
  4. #include "qcom-ipq4019.dtsi"
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/leds/common.h>
  9. / {
  10. model = "ZTE MF282Plus";
  11. compatible = "zte,mf282plus";
  12. aliases {
  13. led-boot = &led_internal;
  14. led-failsafe = &led_internal;
  15. led-running = &led_internal;
  16. led-upgrade = &led_internal;
  17. };
  18. chosen {
  19. /*
  20. * bootargs forced by u-boot bootipq command:
  21. * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
  22. */
  23. bootargs-append = " root=/dev/ubiblock0_1";
  24. };
  25. gpio_export {
  26. compatible = "gpio-export";
  27. #size-cells = <0>;
  28. modem {
  29. gpio-export,name = "modem-reset";
  30. gpio-export,output = <0>;
  31. gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
  32. };
  33. };
  34. leds {
  35. compatible = "gpio-leds";
  36. led_internal: led-0 {
  37. function = LED_FUNCTION_STATUS;
  38. color = <LED_COLOR_ID_BLUE>;
  39. gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
  40. label = "blue:internal_led";
  41. default-state = "keep";
  42. };
  43. led-1 {
  44. function = LED_FUNCTION_WLAN;
  45. color = <LED_COLOR_ID_BLUE>;
  46. gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
  47. linux,default-trigger = "phy0tpt";
  48. };
  49. };
  50. keys {
  51. compatible = "gpio-keys";
  52. wifi {
  53. label = "wifi";
  54. linux,code = <KEY_RFKILL>;
  55. gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
  56. };
  57. reset {
  58. label = "reset";
  59. linux,code = <KEY_RESTART>;
  60. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  61. };
  62. wps {
  63. label = "wps";
  64. linux,code = <KEY_WPS_BUTTON>;
  65. gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
  66. };
  67. };
  68. soc {
  69. rng@22000 {
  70. status = "okay";
  71. };
  72. mdio@90000 {
  73. status = "okay";
  74. pinctrl-0 = <&mdio_pins>;
  75. pinctrl-names = "default";
  76. reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
  77. reset-delay-us = <2000>;
  78. };
  79. tcsr@1949000 {
  80. compatible = "qcom,tcsr";
  81. reg = <0x1949000 0x100>;
  82. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  83. };
  84. tcsr@194b000 {
  85. /* select hostmode */
  86. compatible = "qcom,tcsr";
  87. reg = <0x194b000 0x100>;
  88. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  89. status = "okay";
  90. };
  91. ess_tcsr@1953000 {
  92. compatible = "qcom,tcsr";
  93. reg = <0x1953000 0x1000>;
  94. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  95. };
  96. tcsr@1957000 {
  97. compatible = "qcom,tcsr";
  98. reg = <0x1957000 0x100>;
  99. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  100. };
  101. usb2@60f8800 {
  102. status = "okay";
  103. };
  104. usb3@8af8800 {
  105. status = "okay";
  106. };
  107. crypto@8e3a000 {
  108. status = "okay";
  109. };
  110. watchdog@b017000 {
  111. status = "okay";
  112. };
  113. };
  114. };
  115. &blsp_dma {
  116. status = "okay";
  117. };
  118. &blsp1_spi1 {
  119. pinctrl-0 = <&spi_0_pins>;
  120. pinctrl-names = "default";
  121. status = "okay";
  122. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  123. flash@0 {
  124. /* u-boot is looking for "n25q128a11" property */
  125. compatible = "jedec,spi-nor", "n25q128a11";
  126. #address-cells = <1>;
  127. #size-cells = <1>;
  128. reg = <0>;
  129. spi-max-frequency = <24000000>;
  130. partitions {
  131. compatible = "fixed-partitions";
  132. #address-cells = <1>;
  133. #size-cells = <1>;
  134. partition@0 {
  135. label = "0:SBL1";
  136. reg = <0x0 0x40000>;
  137. read-only;
  138. };
  139. partition@40000 {
  140. label = "0:MIBIB";
  141. reg = <0x40000 0x20000>;
  142. read-only;
  143. };
  144. partition@60000 {
  145. label = "0:QSEE";
  146. reg = <0x60000 0x60000>;
  147. read-only;
  148. };
  149. partition@c0000 {
  150. label = "0:CDT";
  151. reg = <0xc0000 0x10000>;
  152. read-only;
  153. };
  154. partition@d0000 {
  155. label = "0:DDRPARAMS";
  156. reg = <0xd0000 0x10000>;
  157. read-only;
  158. };
  159. partition@e0000 {
  160. label = "0:APPSBLENV";
  161. reg = <0xe0000 0x10000>;
  162. read-only;
  163. };
  164. partition@f0000 {
  165. label = "0:APPSBL";
  166. reg = <0xf0000 0xc0000>;
  167. read-only;
  168. };
  169. partition@1b0000 {
  170. label = "0:reserved1";
  171. reg = <0x1b0000 0x50000>;
  172. read-only;
  173. };
  174. };
  175. };
  176. };
  177. &blsp1_uart1 {
  178. pinctrl-0 = <&serial_pins>;
  179. pinctrl-names = "default";
  180. status = "okay";
  181. };
  182. &cryptobam {
  183. status = "okay";
  184. };
  185. &gmac {
  186. status = "okay";
  187. nvmem-cell-names = "mac-address";
  188. nvmem-cells = <&macaddr_config_0 0>;
  189. };
  190. &nand {
  191. pinctrl-0 = <&nand_pins>;
  192. pinctrl-names = "default";
  193. status = "okay";
  194. nand@0 {
  195. partitions {
  196. compatible = "fixed-partitions";
  197. #address-cells = <1>;
  198. #size-cells = <1>;
  199. partition@0 {
  200. label = "fota-flag";
  201. reg = <0x0 0xa0000>;
  202. read-only;
  203. };
  204. partition@a0000 {
  205. label = "ART";
  206. reg = <0xa0000 0x80000>;
  207. read-only;
  208. nvmem-layout {
  209. compatible = "fixed-layout";
  210. #address-cells = <1>;
  211. #size-cells = <1>;
  212. precal_art_1000: precal@1000 {
  213. reg = <0x1000 0x2f20>;
  214. };
  215. precal_art_5000: precal@5000 {
  216. reg = <0x5000 0x2f20>;
  217. };
  218. };
  219. };
  220. partition@120000 {
  221. label = "mac";
  222. reg = <0x120000 0x80000>;
  223. read-only;
  224. nvmem-layout {
  225. compatible = "fixed-layout";
  226. #address-cells = <1>;
  227. #size-cells = <1>;
  228. macaddr_config_0: macaddr@0 {
  229. compatible = "mac-base";
  230. reg = <0x0 0x6>;
  231. #nvmem-cell-cells = <1>;
  232. };
  233. };
  234. };
  235. partition@1a0000 {
  236. label = "reserved2";
  237. reg = <0x1a0000 0xc0000>;
  238. read-only;
  239. };
  240. partition@260000 {
  241. label = "cfg-param";
  242. reg = <0x260000 0x400000>;
  243. read-only;
  244. };
  245. partition@660000 {
  246. label = "log";
  247. reg = <0x660000 0x400000>;
  248. };
  249. partition@a60000 {
  250. label = "oops";
  251. reg = <0xa60000 0xa0000>;
  252. };
  253. partition@b00000 {
  254. label = "reserved3";
  255. reg = <0xb00000 0x500000>;
  256. read-only;
  257. };
  258. partition@1000000 {
  259. label = "web";
  260. reg = <0x1000000 0x800000>;
  261. };
  262. partition@1800000 {
  263. label = "rootfs";
  264. reg = <0x1800000 0x1d00000>;
  265. };
  266. partition@3500000 {
  267. label = "data";
  268. reg = <0x3500000 0x1900000>;
  269. };
  270. partition@4e00000 {
  271. label = "fota";
  272. reg = <0x4e00000 0x2800000>;
  273. };
  274. partition@7600000 {
  275. label = "extra-cfg";
  276. reg = <0x7600000 0xa00000>;
  277. };
  278. };
  279. };
  280. };
  281. &qpic_bam {
  282. status = "okay";
  283. };
  284. &switch {
  285. status = "okay";
  286. };
  287. &swport4 {
  288. status = "okay";
  289. label = "lan";
  290. };
  291. &tlmm {
  292. i2c_0_pins: i2c_0_pinmux {
  293. mux {
  294. pins = "gpio20", "gpio21";
  295. function = "blsp_i2c0";
  296. bias-disable;
  297. };
  298. };
  299. mdio_pins: mdio_pinmux {
  300. mux_1 {
  301. pins = "gpio6";
  302. function = "mdio";
  303. bias-pull-up;
  304. };
  305. mux_2 {
  306. pins = "gpio7";
  307. function = "mdc";
  308. bias-pull-up;
  309. };
  310. };
  311. nand_pins: nand_pins {
  312. pullups {
  313. pins = "gpio52", "gpio53", "gpio58",
  314. "gpio59";
  315. function = "qpic";
  316. bias-pull-up;
  317. };
  318. pulldowns {
  319. pins = "gpio54", "gpio55", "gpio56",
  320. "gpio57", "gpio60",
  321. "gpio62", "gpio63", "gpio64",
  322. "gpio65", "gpio66", "gpio67",
  323. "gpio69";
  324. function = "qpic";
  325. bias-pull-down;
  326. };
  327. };
  328. serial_pins: serial_pinmux {
  329. mux {
  330. pins = "gpio16", "gpio17";
  331. function = "blsp_uart0";
  332. bias-disable;
  333. };
  334. };
  335. spi_0_pins: spi_0_pinmux {
  336. pinmux {
  337. function = "blsp_spi0";
  338. pins = "gpio13", "gpio14", "gpio15";
  339. drive-strength = <12>;
  340. bias-disable;
  341. };
  342. pinmux_cs {
  343. function = "gpio";
  344. pins = "gpio12";
  345. drive-strength = <2>;
  346. bias-disable;
  347. output-high;
  348. };
  349. };
  350. };
  351. &usb2_hs_phy {
  352. status = "okay";
  353. };
  354. &usb3_ss_phy {
  355. status = "okay";
  356. };
  357. &usb3_hs_phy {
  358. status = "okay";
  359. };
  360. /*
  361. * The MD5 sum of the board file of the MF286D is identical to the board
  362. * file in the OEM firmware
  363. */
  364. &wifi0 {
  365. status = "okay";
  366. nvmem-cell-names = "pre-calibration", "mac-address";
  367. nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 1>;
  368. qcom,ath10k-calibration-variant = "zte,mf286d";
  369. };
  370. /*
  371. * The MD5 sum of the board file of the MF286D is identical to the board
  372. * file in the OEM firmware
  373. */
  374. &wifi1 {
  375. status = "okay";
  376. nvmem-cell-names = "pre-calibration", "mac-address";
  377. nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 1>;
  378. qcom,ath10k-calibration-variant = "zte,mf286d";
  379. };