2
0

qcom-ipq4019-oap100.dts 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342
  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "EdgeCore OAP-100";
  8. compatible = "edgecore,oap100";
  9. aliases {
  10. led-boot = &led_system;
  11. led-failsafe = &led_system;
  12. led-running = &led_system;
  13. led-upgrade = &led_system;
  14. };
  15. chosen {
  16. bootargs-append = " root=/dev/ubiblock0_1";
  17. };
  18. soc {
  19. mdio@90000 {
  20. status = "okay";
  21. pinctrl-0 = <&mdio_pins>;
  22. pinctrl-names = "default";
  23. };
  24. tcsr@1949000 {
  25. compatible = "qcom,tcsr";
  26. reg = <0x1949000 0x100>;
  27. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  28. };
  29. ess_tcsr@1953000 {
  30. compatible = "qcom,tcsr";
  31. reg = <0x1953000 0x1000>;
  32. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  33. };
  34. tcsr@1957000 {
  35. compatible = "qcom,tcsr";
  36. reg = <0x1957000 0x100>;
  37. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  38. };
  39. tcsr@194b000 {
  40. /* select hostmode */
  41. compatible = "qcom,tcsr";
  42. reg = <0x194b000 0x100>;
  43. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  44. status = "okay";
  45. };
  46. usb2@60f8800 {
  47. status = "okay";
  48. dwc3@6000000 {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. usb2_port1: port@1 {
  52. reg = <1>;
  53. #trigger-source-cells = <0>;
  54. };
  55. };
  56. };
  57. usb3@8af8800 {
  58. status = "okay";
  59. dwc3@8a00000 {
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. usb3_port1: port@1 {
  63. reg = <1>;
  64. #trigger-source-cells = <0>;
  65. };
  66. usb3_port2: port@2 {
  67. reg = <2>;
  68. #trigger-source-cells = <0>;
  69. };
  70. };
  71. };
  72. crypto@8e3a000 {
  73. status = "okay";
  74. };
  75. watchdog@b017000 {
  76. status = "okay";
  77. };
  78. };
  79. key {
  80. compatible = "gpio-keys";
  81. button@1 {
  82. label = "reset";
  83. linux,code = <KEY_RESTART>;
  84. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  85. linux,input-type = <1>;
  86. };
  87. };
  88. leds {
  89. compatible = "gpio-leds";
  90. led_system: led_system {
  91. label = "green:system";
  92. gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
  93. };
  94. led_2g {
  95. label = "blue:wlan2g";
  96. gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
  97. };
  98. led_5g {
  99. label = "blue:wlan5g";
  100. gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
  101. };
  102. };
  103. gpio_export {
  104. compatible = "gpio-export";
  105. #size-cells = <0>;
  106. usb {
  107. gpio-export,name = "usb-power";
  108. gpio-export,output = <1>;
  109. gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
  110. };
  111. poe {
  112. gpio-export,name = "poe-power";
  113. gpio-export,output = <0>;
  114. gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
  115. };
  116. };
  117. };
  118. &tlmm {
  119. serial_0_pins: serial_pinmux {
  120. mux {
  121. pins = "gpio16", "gpio17";
  122. function = "blsp_uart0";
  123. bias-disable;
  124. };
  125. };
  126. spi_0_pins: spi_0_pinmux {
  127. pinmux {
  128. function = "blsp_spi0";
  129. pins = "gpio13", "gpio14", "gpio15";
  130. drive-strength = <12>;
  131. bias-disable;
  132. };
  133. pinmux_cs {
  134. function = "gpio";
  135. pins = "gpio12";
  136. drive-strength = <2>;
  137. bias-disable;
  138. output-high;
  139. };
  140. };
  141. nand_pins: nand_pins {
  142. pullups {
  143. pins = "gpio53", "gpio58", "gpio59";
  144. function = "qpic";
  145. bias-pull-up;
  146. };
  147. pulldowns {
  148. pins = "gpio54", "gpio55", "gpio56",
  149. "gpio57", "gpio60", "gpio61",
  150. "gpio62", "gpio63", "gpio64",
  151. "gpio65", "gpio66", "gpio67",
  152. "gpio68", "gpio69";
  153. function = "qpic";
  154. bias-pull-down;
  155. };
  156. };
  157. mdio_pins: mdio_pinmux {
  158. mux_1 {
  159. pins = "gpio6";
  160. function = "mdio";
  161. bias-pull-up;
  162. };
  163. mux_2 {
  164. pins = "gpio7";
  165. function = "mdc";
  166. bias-pull-up;
  167. };
  168. };
  169. };
  170. &cryptobam {
  171. status = "okay";
  172. };
  173. &blsp1_spi1 {
  174. pinctrl-0 = <&spi_0_pins>;
  175. pinctrl-names = "default";
  176. status = "okay";
  177. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
  178. flash@0 {
  179. #address-cells = <1>;
  180. #size-cells = <1>;
  181. compatible = "jedec,spi-nor";
  182. reg = <0>;
  183. linux,modalias = "m25p80", "gd25q256";
  184. spi-max-frequency = <24000000>;
  185. partitions {
  186. compatible = "fixed-partitions";
  187. #address-cells = <1>;
  188. #size-cells = <1>;
  189. partition0@0 {
  190. label = "0:SBL1";
  191. reg = <0x00000000 0x00040000>;
  192. read-only;
  193. };
  194. partition1@40000 {
  195. label = "0:MIBIB";
  196. reg = <0x00040000 0x00020000>;
  197. read-only;
  198. };
  199. partition2@60000 {
  200. label = "0:QSEE";
  201. reg = <0x00060000 0x00060000>;
  202. read-only;
  203. };
  204. partition3@c0000 {
  205. label = "0:CDT";
  206. reg = <0x000c0000 0x00010000>;
  207. read-only;
  208. };
  209. partition4@d0000 {
  210. label = "0:DDRPARAMS";
  211. reg = <0x000d0000 0x00010000>;
  212. read-only;
  213. };
  214. partition5@e0000 {
  215. label = "0:APPSBLENV";
  216. reg = <0x000e0000 0x00010000>;
  217. read-only;
  218. };
  219. partition6@f0000 {
  220. label = "0:APPSBL";
  221. reg = <0x000f0000 0x00080000>;
  222. read-only;
  223. };
  224. partition7@170000 {
  225. label = "0:ART";
  226. reg = <0x00170000 0x00010000>;
  227. read-only;
  228. nvmem-layout {
  229. compatible = "fixed-layout";
  230. #address-cells = <1>;
  231. #size-cells = <1>;
  232. precal_art_1000: precal@1000 {
  233. reg = <0x1000 0x2f20>;
  234. };
  235. precal_art_5000: precal@5000 {
  236. reg = <0x5000 0x2f20>;
  237. };
  238. };
  239. };
  240. };
  241. };
  242. };
  243. &nand {
  244. pinctrl-0 = <&nand_pins>;
  245. pinctrl-names = "default";
  246. status = "okay";
  247. nand@0 {
  248. partitions {
  249. compatible = "fixed-partitions";
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. partition@0 {
  253. label = "rootfs";
  254. reg = <0x00000000 0x4000000>;
  255. };
  256. };
  257. };
  258. };
  259. &blsp_dma {
  260. status = "okay";
  261. };
  262. &blsp1_uart1 {
  263. pinctrl-0 = <&serial_0_pins>;
  264. pinctrl-names = "default";
  265. status = "okay";
  266. };
  267. &qpic_bam {
  268. status = "okay";
  269. };
  270. &wifi0 {
  271. status = "okay";
  272. nvmem-cell-names = "pre-calibration";
  273. nvmem-cells = <&precal_art_1000>;
  274. qcom,ath10k-calibration-variant = "Edgecore OAP100";
  275. };
  276. &wifi1 {
  277. status = "okay";
  278. nvmem-cell-names = "pre-calibration";
  279. nvmem-cells = <&precal_art_5000>;
  280. qcom,ath10k-calibration-variant = "Edgecore OAP100";
  281. };
  282. &usb3_ss_phy {
  283. status = "okay";
  284. };
  285. &usb3_hs_phy {
  286. status = "okay";
  287. };
  288. &usb2_hs_phy {
  289. status = "okay";
  290. };