qcom-ipq4019-r619ac.dtsi 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. #include <dt-bindings/leds/common.h>
  7. / {
  8. chosen {
  9. bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  10. };
  11. aliases {
  12. led-boot = &led_sys;
  13. led-failsafe = &led_sys;
  14. led-running = &led_sys;
  15. led-upgrade = &led_sys;
  16. };
  17. soc {
  18. rng@22000 {
  19. status = "okay";
  20. };
  21. mdio@90000 {
  22. status = "okay";
  23. pinctrl-0 = <&mdio_pins>;
  24. pinctrl-names = "default";
  25. };
  26. tcsr@1949000 {
  27. compatible = "qcom,tcsr";
  28. reg = <0x1949000 0x100>;
  29. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  30. };
  31. tcsr@194b000 {
  32. compatible = "qcom,tcsr";
  33. reg = <0x194b000 0x100>;
  34. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  35. };
  36. ess_tcsr@1953000 {
  37. compatible = "qcom,tcsr";
  38. reg = <0x1953000 0x1000>;
  39. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  40. };
  41. tcsr@1957000 {
  42. compatible = "qcom,tcsr";
  43. reg = <0x1957000 0x100>;
  44. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  45. };
  46. usb2@60f8800 {
  47. status = "okay";
  48. };
  49. usb3@8af8800 {
  50. status = "okay";
  51. };
  52. crypto@8e3a000 {
  53. status = "okay";
  54. };
  55. watchdog@b017000 {
  56. status = "okay";
  57. };
  58. };
  59. leds {
  60. compatible = "gpio-leds";
  61. led_sys: led-0 {
  62. gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
  63. color = <LED_COLOR_ID_BLUE>;
  64. function = LED_FUNCTION_POWER;
  65. };
  66. led-1 {
  67. gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
  68. linux,default-trigger = "phy0tpt";
  69. color = <LED_COLOR_ID_BLUE>;
  70. function = LED_FUNCTION_WLAN;
  71. function-enumerator = <0>;
  72. };
  73. led-2 {
  74. gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  75. linux,default-trigger = "phy1tpt";
  76. color = <LED_COLOR_ID_BLUE>;
  77. function = LED_FUNCTION_WLAN;
  78. function-enumerator = <1>;
  79. };
  80. };
  81. keys {
  82. compatible = "gpio-keys";
  83. reset {
  84. label = "reset";
  85. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  86. linux,code = <KEY_RESTART>;
  87. };
  88. };
  89. };
  90. &blsp_dma {
  91. status = "okay";
  92. };
  93. &blsp1_spi1 {
  94. status = "okay";
  95. flash@0 {
  96. reg = <0>;
  97. compatible = "jedec,spi-nor";
  98. spi-max-frequency = <24000000>;
  99. partitions {
  100. compatible = "fixed-partitions";
  101. #address-cells = <1>;
  102. #size-cells = <1>;
  103. partition@0 {
  104. label = "SBL1";
  105. reg = <0x0 0x40000>;
  106. read-only;
  107. };
  108. partition@40000 {
  109. label = "MIBIB";
  110. reg = <0x40000 0x20000>;
  111. read-only;
  112. };
  113. partition@60000 {
  114. label = "QSEE";
  115. reg = <0x60000 0x60000>;
  116. read-only;
  117. };
  118. partition@c0000 {
  119. label = "CDT";
  120. reg = <0xc0000 0x10000>;
  121. read-only;
  122. };
  123. partition@d0000 {
  124. label = "DDRPARAMS";
  125. reg = <0xd0000 0x10000>;
  126. read-only;
  127. };
  128. partition@e0000 {
  129. label = "APPSBLENV";
  130. reg = <0xe0000 0x10000>;
  131. read-only;
  132. };
  133. partition@f0000 {
  134. label = "APPSBL";
  135. reg = <0xf0000 0x80000>;
  136. read-only;
  137. };
  138. partition@170000 {
  139. label = "ART";
  140. reg = <0x170000 0x10000>;
  141. read-only;
  142. nvmem-layout {
  143. compatible = "fixed-layout";
  144. #address-cells = <1>;
  145. #size-cells = <1>;
  146. precal_art_1000: precal@1000 {
  147. reg = <0x1000 0x2f20>;
  148. };
  149. precal_art_5000: precal@5000 {
  150. reg = <0x5000 0x2f20>;
  151. };
  152. };
  153. };
  154. };
  155. };
  156. };
  157. &nand {
  158. status = "okay";
  159. nand@0 {
  160. partitions {
  161. compatible = "fixed-partitions";
  162. #address-cells = <1>;
  163. #size-cells = <1>;
  164. nand_rootfs: partition@0 {
  165. label = "ubi";
  166. /* reg defined in 64M/128M variant dts. */
  167. };
  168. };
  169. };
  170. };
  171. &blsp1_uart1 {
  172. pinctrl-0 = <&serial_0_pins>;
  173. pinctrl-names = "default";
  174. status = "okay";
  175. };
  176. &cryptobam {
  177. status = "okay";
  178. };
  179. &pcie0 {
  180. status = "okay";
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&pcie_pins>;
  183. perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
  184. wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
  185. /* Free slot for use */
  186. bridge@0,0 {
  187. reg = <0x00000000 0 0 0 0>;
  188. #address-cells = <3>;
  189. #size-cells = <2>;
  190. ranges;
  191. };
  192. };
  193. &qpic_bam {
  194. status = "okay";
  195. };
  196. &sdhci {
  197. pinctrl-0 = <&sd_0_pins>;
  198. pinctrl-names = "default";
  199. vqmmc-supply = <&vqmmc>;
  200. status = "okay";
  201. };
  202. &tlmm {
  203. pcie_pins: pcie_pinmux {
  204. mux {
  205. pins = "gpio2";
  206. function = "gpio";
  207. output-low;
  208. bias-pull-down;
  209. };
  210. };
  211. mdio_pins: mdio_pinmux {
  212. mux_1 {
  213. pins = "gpio6";
  214. function = "mdio";
  215. bias-pull-up;
  216. };
  217. mux_2 {
  218. pins = "gpio7";
  219. function = "mdc";
  220. bias-pull-up;
  221. };
  222. };
  223. sd_0_pins: sd_0_pinmux {
  224. mux_1 {
  225. pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
  226. function = "sdio";
  227. drive-strength = <10>;
  228. };
  229. mux_2 {
  230. pins = "gpio27";
  231. function = "sdio";
  232. drive-strength = <16>;
  233. };
  234. };
  235. serial_0_pins: serial0-pinmux {
  236. mux {
  237. pins = "gpio16", "gpio17";
  238. function = "blsp_uart0";
  239. bias-disable;
  240. };
  241. };
  242. };
  243. &ethphy0 {
  244. qcom,single-led-1000;
  245. qcom,single-led-100;
  246. qcom,single-led-10;
  247. };
  248. &ethphy1 {
  249. qcom,single-led-1000;
  250. qcom,single-led-100;
  251. qcom,single-led-10;
  252. };
  253. &ethphy2 {
  254. qcom,single-led-1000;
  255. qcom,single-led-100;
  256. qcom,single-led-10;
  257. };
  258. &ethphy3 {
  259. qcom,single-led-1000;
  260. qcom,single-led-100;
  261. qcom,single-led-10;
  262. };
  263. &ethphy4 {
  264. qcom,single-led-1000;
  265. qcom,single-led-100;
  266. qcom,single-led-10;
  267. };
  268. &gmac {
  269. status = "okay";
  270. };
  271. &switch {
  272. status = "okay";
  273. };
  274. &swport1 {
  275. status = "okay";
  276. label = "lan4";
  277. };
  278. &swport2 {
  279. status = "okay";
  280. label = "lan3";
  281. };
  282. &swport3 {
  283. status = "okay";
  284. label = "lan2";
  285. };
  286. &swport4 {
  287. status = "okay";
  288. label = "lan1";
  289. };
  290. &swport5 {
  291. status = "okay";
  292. };
  293. &usb3_ss_phy {
  294. status = "okay";
  295. };
  296. &usb3_hs_phy {
  297. status = "okay";
  298. };
  299. &usb2_hs_phy {
  300. status = "okay";
  301. };
  302. &vqmmc {
  303. status = "okay";
  304. };
  305. &wifi0 {
  306. status = "okay";
  307. nvmem-cell-names = "pre-calibration";
  308. nvmem-cells = <&precal_art_1000>;
  309. qcom,ath10k-calibration-variant = "P&W-R619AC";
  310. };
  311. &wifi1 {
  312. status = "okay";
  313. nvmem-cell-names = "pre-calibration";
  314. nvmem-cells = <&precal_art_5000>;
  315. qcom,ath10k-calibration-variant = "P&W-R619AC";
  316. };