qcom-ipq4029-ap-303h.dts 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only OR MIT
  2. #include "qcom-ipq4019.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include <dt-bindings/soc/qcom,tcsr.h>
  6. / {
  7. model = "Aruba AP-303H";
  8. compatible = "aruba,ap-303h";
  9. aliases {
  10. led-boot = &led_system_green;
  11. led-failsafe = &led_system_red;
  12. led-running = &led_system_green;
  13. led-upgrade = &led_system_amber;
  14. };
  15. memory {
  16. device_type = "memory";
  17. reg = <0x80000000 0x10000000>;
  18. };
  19. soc {
  20. rng@22000 {
  21. status = "okay";
  22. };
  23. mdio@90000 {
  24. status = "okay";
  25. pinctrl-0 = <&mdio_pins>;
  26. pinctrl-names = "default";
  27. reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
  28. reset-delay-us = <2000>;
  29. };
  30. counter@4a1000 {
  31. compatible = "qcom,qca-gcnt";
  32. reg = <0x4a1000 0x4>;
  33. };
  34. ess_tcsr@1953000 {
  35. compatible = "qcom,tcsr";
  36. reg = <0x1953000 0x1000>;
  37. qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  38. };
  39. tcsr@1949000 {
  40. compatible = "qcom,tcsr";
  41. reg = <0x1949000 0x100>;
  42. qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  43. };
  44. tcsr@194b000 {
  45. compatible = "qcom,tcsr";
  46. reg = <0x194b000 0x100>;
  47. qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  48. };
  49. tcsr@1957000 {
  50. compatible = "qcom,tcsr";
  51. reg = <0x1957000 0x100>;
  52. qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  53. };
  54. usb2@60f8800 {
  55. status = "okay";
  56. };
  57. crypto@8e3a000 {
  58. status = "okay";
  59. };
  60. watchdog@b017000 {
  61. status = "okay";
  62. };
  63. i2c_0: i2c@78b7000 {
  64. pinctrl-0 = <&i2c_0_pins>;
  65. pinctrl-names = "default";
  66. status = "okay";
  67. tpm@29 {
  68. /* No Driver */
  69. compatible = "atmel,at97sc3203";
  70. reg = <0x29>;
  71. read-only;
  72. };
  73. power-monitor@40 {
  74. /* No driver */
  75. compatible = "isl,isl28022";
  76. reg = <0x40>;
  77. };
  78. };
  79. };
  80. leds {
  81. compatible = "gpio-leds";
  82. wifi_green {
  83. label = "green:wifi";
  84. gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
  85. linux,default-trigger = "phy0tpt";
  86. };
  87. wifi_amber {
  88. label = "amber:wifi";
  89. gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
  90. linux,default-trigger = "phy1tpt";
  91. };
  92. pse {
  93. label = "green:pse";
  94. gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
  95. };
  96. led_system_red: system_red {
  97. label = "red:system";
  98. gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
  99. };
  100. led_system_green: system_green {
  101. label = "green:system";
  102. gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
  103. };
  104. led_system_amber: system_amber {
  105. label = "amber:system";
  106. gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
  107. };
  108. };
  109. keys {
  110. compatible = "gpio-keys";
  111. reset {
  112. label = "Reset button";
  113. gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  114. linux,code = <KEY_RESTART>;
  115. };
  116. };
  117. };
  118. &blsp_dma {
  119. status = "okay";
  120. };
  121. &blsp1_uart1 {
  122. pinctrl-0 = <&serial_0_pins>;
  123. pinctrl-names = "default";
  124. status = "okay";
  125. };
  126. &blsp1_uart2 {
  127. /* Texas Instruments CC2540T BLE radio */
  128. pinctrl-0 = <&serial_1_pins>;
  129. pinctrl-names = "default";
  130. status = "okay";
  131. };
  132. &cryptobam {
  133. status = "okay";
  134. };
  135. &qpic_bam {
  136. status = "okay";
  137. };
  138. &tlmm {
  139. /*
  140. * In addition to the Pins listed below,
  141. * the following GPIOs have "features":
  142. * 39 - out - active low to force HW reset
  143. * 32 - out - active low to reset TPM
  144. * 43 - out - active low to reset BLE radio
  145. * 41 - out - pulse to set warm reset status
  146. * 34 - out - active low to enable PSE port
  147. * 22 - in - active low when 802.3at powered
  148. * 29 - in - active high when DC powered
  149. * 40 - in - active low when reset due to cold HW reset
  150. * 30 - in - active low when USB overcurrent detected
  151. * 35 - in - interrupt line for power monitor chip
  152. * 31 - in - active low when PSE port active
  153. */
  154. mdio_pins: mdio_pinmux {
  155. mux_1 {
  156. pins = "gpio6";
  157. function = "mdio";
  158. bias-pull-up;
  159. };
  160. mux_2 {
  161. pins = "gpio7";
  162. function = "mdc";
  163. bias-pull-up;
  164. };
  165. };
  166. spi_0_pins: spi_0_pinmux {
  167. pin {
  168. function = "blsp_spi0";
  169. pins = "gpio13", "gpio14", "gpio15";
  170. drive-strength = <12>;
  171. bias-disable;
  172. };
  173. pin_cs {
  174. function = "gpio";
  175. pins = "gpio12", "gpio59";
  176. drive-strength = <2>;
  177. bias-disable;
  178. output-high;
  179. };
  180. };
  181. i2c_0_pins: i2c_0_pinmux {
  182. mux {
  183. pins = "gpio20", "gpio21";
  184. function = "blsp_i2c0";
  185. drive-strength = <4>;
  186. bias-disable;
  187. };
  188. };
  189. serial_0_pins: serial_0_pinmux {
  190. mux {
  191. pins = "gpio16", "gpio17";
  192. function = "blsp_uart0";
  193. bias-disable;
  194. };
  195. };
  196. serial_1_pins: serial_1_pinmux {
  197. mux {
  198. pins = "gpio8", "gpio9";
  199. function = "blsp_uart1";
  200. bias-disable;
  201. };
  202. };
  203. usb-power {
  204. line-name = "USB-power";
  205. gpios = <23 GPIO_ACTIVE_HIGH>;
  206. gpio-hog;
  207. output-high;
  208. };
  209. };
  210. &blsp1_spi1 {
  211. pinctrl-0 = <&spi_0_pins>;
  212. pinctrl-names = "default";
  213. status = "okay";
  214. cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
  215. flash@0 {
  216. compatible = "jedec,spi-nor";
  217. reg = <0>;
  218. spi-max-frequency = <24000000>;
  219. partitions {
  220. compatible = "fixed-partitions";
  221. #address-cells = <1>;
  222. #size-cells = <1>;
  223. /*
  224. * There is no partition map for the NOR flash
  225. * in the stock firmware.
  226. *
  227. * All partitions here are based on offsets
  228. * found in the U-Boot GPL code and information
  229. * from smem.
  230. */
  231. partition@0 {
  232. label = "sbl1";
  233. reg = <0x0 0x40000>;
  234. read-only;
  235. };
  236. partition@40000 {
  237. label = "mibib";
  238. reg = <0x40000 0x20000>;
  239. read-only;
  240. };
  241. partition@60000 {
  242. label = "qsee";
  243. reg = <0x60000 0x60000>;
  244. read-only;
  245. };
  246. partition@c0000 {
  247. label = "cdt";
  248. reg = <0xc0000 0x10000>;
  249. read-only;
  250. };
  251. partition@d0000 {
  252. label = "ddrparams";
  253. reg = <0xd0000 0x10000>;
  254. read-only;
  255. };
  256. partition@e0000 {
  257. label = "appsblenv";
  258. reg = <0xe0000 0x10000>;
  259. read-only;
  260. };
  261. partition@f0000 {
  262. label = "appsbl";
  263. reg = <0xf0000 0x100000>;
  264. read-only;
  265. };
  266. partition@1e0000 {
  267. label = "ART";
  268. reg = <0x1f0000 0x10000>;
  269. read-only;
  270. nvmem-layout {
  271. compatible = "fixed-layout";
  272. #address-cells = <1>;
  273. #size-cells = <1>;
  274. precal_art_1000: precal@1000 {
  275. reg = <0x1000 0x2f20>;
  276. };
  277. precal_art_5000: precal@5000 {
  278. reg = <0x5000 0x2f20>;
  279. };
  280. };
  281. };
  282. partition@1f0000 {
  283. label = "osss";
  284. reg = <0x200000 0x170000>;
  285. read-only;
  286. };
  287. partition@200000 {
  288. label = "pds";
  289. reg = <0x370000 0x10000>;
  290. read-only;
  291. };
  292. partition@380000 {
  293. label = "apcd";
  294. reg = <0x380000 0x10000>;
  295. read-only;
  296. };
  297. partition@390000 {
  298. label = "mfginfo";
  299. reg = <0x390000 0x10000>;
  300. read-only;
  301. nvmem-layout {
  302. compatible = "fixed-layout";
  303. #address-cells = <1>;
  304. #size-cells = <1>;
  305. macaddr_mfginfo_1d: macaddr@1d {
  306. reg = <0x1d 0x6>;
  307. };
  308. macaddr_mfginfo_45: macaddr@45 {
  309. compatible = "mac-base";
  310. reg = <0x45 0x6>;
  311. #nvmem-cell-cells = <1>;
  312. };
  313. };
  314. };
  315. partition@3a0000 {
  316. label = "fcache";
  317. reg = <0x3a0000 0x10000>;
  318. read-only;
  319. };
  320. partition@3b0000 {
  321. /* Called osss1 in smem */
  322. label = "u-boot-env-bak";
  323. reg = <0x3b0000 0x10000>;
  324. read-only;
  325. };
  326. partition@3f0000 {
  327. label = "u-boot-env";
  328. reg = <0x3c0000 0x40000>;
  329. read-only;
  330. };
  331. };
  332. };
  333. flash@1 {
  334. status = "okay";
  335. compatible = "spi-nand";
  336. reg = <1>;
  337. spi-max-frequency = <24000000>;
  338. partitions {
  339. compatible = "fixed-partitions";
  340. #address-cells = <1>;
  341. #size-cells = <1>;
  342. partition@0 {
  343. /* 'aos0' in Aruba firmware */
  344. label = "aos0";
  345. reg = <0x0 0x2000000>;
  346. read-only;
  347. };
  348. partition@2000000 {
  349. /* 'aos1' in Aruba firmware */
  350. label = "ubi";
  351. reg = <0x2000000 0x2000000>;
  352. };
  353. partition@4000000 {
  354. label = "aruba-ubifs";
  355. reg = <0x4000000 0x4000000>;
  356. read-only;
  357. };
  358. };
  359. };
  360. };
  361. &usb2_hs_phy {
  362. status = "okay";
  363. };
  364. &gmac {
  365. status = "okay";
  366. };
  367. &switch {
  368. status = "okay";
  369. };
  370. &swport2 {
  371. status = "okay";
  372. label = "lan1";
  373. };
  374. &swport3 {
  375. status = "okay";
  376. label = "lan2";
  377. };
  378. &swport4 {
  379. status = "okay";
  380. label = "lan3";
  381. };
  382. &swport5 {
  383. status = "okay";
  384. label = "wan";
  385. };
  386. &wifi0 {
  387. status = "okay";
  388. nvmem-cell-names = "pre-calibration", "mac-address";
  389. nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
  390. qcom,ath10k-calibration-variant = "Aruba-AP-303";
  391. };
  392. &wifi1 {
  393. status = "okay";
  394. nvmem-cell-names = "pre-calibration", "mac-address";
  395. nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
  396. qcom,ath10k-calibration-variant = "Aruba-AP-303";
  397. };