1004-gmac-enable-napi.patch 3.0 KB

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  1. Index: linux-2.6.23.16/drivers/net/sl351x_gmac.c
  2. ===================================================================
  3. --- linux-2.6.23.16.orig/drivers/net/sl351x_gmac.c 2008-03-15 16:59:23.361457295 +0200
  4. +++ linux-2.6.23.16/drivers/net/sl351x_gmac.c 2008-03-15 17:00:32.365389612 +0200
  5. @@ -68,9 +68,11 @@
  6. #include <linux/ip.h>
  7. #endif
  8. +/* Enables NAPI unconditionally */
  9. +#define CONFIG_SL_NAPI 1
  10. +
  11. // #define SL351x_TEST_WORKAROUND
  12. #ifdef CONFIG_SL351x_NAT
  13. -#define CONFIG_SL_NAPI 1
  14. #endif
  15. #define GMAX_TX_INTR_DISABLED 1
  16. #define DO_HW_CHKSUM 1
  17. @@ -124,12 +126,17 @@
  18. *************************************************************/
  19. static int gmac_initialized = 0;
  20. TOE_INFO_T toe_private_data;
  21. -//static int do_again = 0;
  22. +static int do_again = 0;
  23. spinlock_t gmac_fq_lock;
  24. unsigned int FLAG_SWITCH;
  25. static unsigned int next_tick = 3 * HZ;
  26. -static unsigned char eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
  27. +static unsigned char eth_mac[CONFIG_MAC_NUM][6]= {
  28. + {0x00,0x11,0x11,0x87,0x87,0x87},
  29. +#if GMAC_NUM != 1
  30. + {0x00,0x22,0x22,0xab,0xab,0xab}
  31. +#endif
  32. +};
  33. #undef CONFIG_SL351x_RXTOE
  34. extern NAT_CFG_T nat_cfg;
  35. @@ -2443,7 +2450,8 @@
  36. toe = (TOE_INFO_T *)&toe_private_data;
  37. // handle NAPI
  38. #ifdef CONFIG_SL_NAPI
  39. -if (storlink_ctl.pauseoff == 1)
  40. + /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
  41. +if (1)
  42. {
  43. /* disable GMAC interrupt */
  44. //toe_gmac_disable_interrupt(tp->irq);
  45. @@ -2530,7 +2538,7 @@
  46. {
  47. if (likely(netif_rx_schedule_prep(dev)))
  48. {
  49. - unsigned int data32;
  50. + // unsigned int data32;
  51. // disable GMAC-0 rx interrupt
  52. // class-Q & TOE-Q are implemented in future
  53. //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
  54. @@ -2563,7 +2571,7 @@
  55. {
  56. if (likely(netif_rx_schedule_prep(dev)))
  57. {
  58. - unsigned int data32;
  59. + // unsigned int data32;
  60. // disable GMAC-0 rx interrupt
  61. // class-Q & TOE-Q are implemented in future
  62. //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
  63. @@ -4217,7 +4225,7 @@
  64. GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
  65. unsigned int status4;
  66. volatile DMA_RWPTR_T fq_rwptr;
  67. - int max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
  68. + // int max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
  69. //unsigned long rx_old_bytes;
  70. struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
  71. //unsigned long long rx_time;
  72. @@ -4479,7 +4487,7 @@
  73. if (rwptr.bits.rptr == rwptr.bits.wptr)
  74. {
  75. - unsigned int data32;
  76. + // unsigned int data32;
  77. //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr] rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
  78. /* Receive descriptor is empty now */