K2G.dts 2.1 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "phicomm,k2g", "ralink,mt7620a-soc";
  7. model = "Phicomm K2G";
  8. aliases {
  9. led-status = &led_blue;
  10. serial0 = &uartlite;
  11. };
  12. gpio-leds {
  13. compatible = "gpio-leds";
  14. led_blue: blue {
  15. label = "k2g:blue:status";
  16. gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  17. };
  18. yellow {
  19. label = "k2g:yellow:status";
  20. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  21. };
  22. red {
  23. label = "k2g:red:status";
  24. gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  25. };
  26. };
  27. gpio-keys-polled {
  28. compatible = "gpio-keys-polled";
  29. poll-interval = <20>;
  30. reset {
  31. label = "reset";
  32. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  33. linux,code = <KEY_RESTART>;
  34. };
  35. };
  36. };
  37. &spi0 {
  38. status = "okay";
  39. m25p80@0 {
  40. compatible = "jedec,spi-nor";
  41. reg = <0>;
  42. spi-max-frequency = <24000000>;
  43. partitions {
  44. compatible = "fixed-partitions";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. partition@0 {
  48. reg = <0x0 0x30000>;
  49. label = "u-boot";
  50. read-only;
  51. };
  52. partition@30000 {
  53. reg = <0x30000 0x10000>;
  54. label = "u-boot-env";
  55. read-only;
  56. };
  57. factory: partition@40000 {
  58. reg = <0x40000 0x10000>;
  59. label = "factory";
  60. read-only;
  61. };
  62. partition@50000 {
  63. reg = <0x50000 0x50000>;
  64. label = "permanent_config";
  65. read-only;
  66. };
  67. partition@a0000 {
  68. reg = <0xa0000 0x760000>;
  69. label = "firmware";
  70. };
  71. };
  72. };
  73. };
  74. &pinctrl {
  75. state_default: pinctrl0 {
  76. gpio {
  77. ralink,group = "i2c", "uartf";
  78. ralink,function = "gpio";
  79. };
  80. };
  81. };
  82. &ethernet {
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&rgmii2_pins &mdio_pins>;
  85. mtd-mac-address = <&factory 0x28>;
  86. mediatek,portmap = "llllw";
  87. port@5 {
  88. status = "okay";
  89. phy-handle = <&phy5>;
  90. phy-mode = "rgmii";
  91. };
  92. mdio-bus {
  93. status = "okay";
  94. phy5: ethernet-phy@5 {
  95. reg = <5>;
  96. phy-mode = "rgmii";
  97. };
  98. };
  99. };
  100. &pcie {
  101. status = "okay";
  102. };
  103. &pcie0 {
  104. mt76@0,0 {
  105. reg = <0x0000 0 0 0 0>;
  106. mediatek,mtd-eeprom = <&factory 0x8000>;
  107. ieee80211-freq-limit = <5000000 6000000>;
  108. };
  109. };
  110. &wmac {
  111. ralink,mtd-eeprom = <&factory 0>;
  112. pinctrl-names = "default";
  113. pinctrl-0 = <&pa_pins>;
  114. };