104-v5.18-mtd-rawnand-brcmnand-Allow-working-without-interrupts.patch 2.7 KB

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  1. From: Florian Fainelli <[email protected]>
  2. Subject: [PATCH v3 5/9] mtd: rawnand: brcmnand: Allow working without interrupts
  3. Date: Fri, 07 Jan 2022 10:46:10 -0800
  4. Content-Type: text/plain; charset="utf-8"
  5. The BCMA devices include the brcmnand controller but they do not wire up
  6. any interrupt line, allow the main interrupt to be optional and update
  7. the completion path to also check for the lack of an interrupt line.
  8. Signed-off-by: Florian Fainelli <[email protected]>
  9. ---
  10. drivers/mtd/nand/raw/brcmnand/brcmnand.c | 52 +++++++++++-------------
  11. 1 file changed, 24 insertions(+), 28 deletions(-)
  12. --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
  13. +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
  14. @@ -216,7 +216,7 @@ struct brcmnand_controller {
  15. void __iomem *nand_base;
  16. void __iomem *nand_fc; /* flash cache */
  17. void __iomem *flash_dma_base;
  18. - unsigned int irq;
  19. + int irq;
  20. unsigned int dma_irq;
  21. int nand_version;
  22. @@ -1650,7 +1650,7 @@ static bool brcmstb_nand_wait_for_comple
  23. bool err = false;
  24. int sts;
  25. - if (mtd->oops_panic_write) {
  26. + if (mtd->oops_panic_write || ctrl->irq < 0) {
  27. /* switch to interrupt polling and PIO mode */
  28. disable_ctrl_irqs(ctrl);
  29. sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
  30. @@ -3191,33 +3191,29 @@ int brcmnand_probe(struct platform_devic
  31. }
  32. /* IRQ */
  33. - ctrl->irq = platform_get_irq(pdev, 0);
  34. - if ((int)ctrl->irq < 0) {
  35. - dev_err(dev, "no IRQ defined\n");
  36. - ret = -ENODEV;
  37. - goto err;
  38. - }
  39. -
  40. - /*
  41. - * Some SoCs integrate this controller (e.g., its interrupt bits) in
  42. - * interesting ways
  43. - */
  44. - if (soc) {
  45. - ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
  46. - DRV_NAME, ctrl);
  47. -
  48. - /* Enable interrupt */
  49. - ctrl->soc->ctlrdy_ack(ctrl->soc);
  50. - ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
  51. - } else {
  52. - /* Use standard interrupt infrastructure */
  53. - ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
  54. - DRV_NAME, ctrl);
  55. - }
  56. - if (ret < 0) {
  57. - dev_err(dev, "can't allocate IRQ %d: error %d\n",
  58. - ctrl->irq, ret);
  59. - goto err;
  60. + ctrl->irq = platform_get_irq_optional(pdev, 0);
  61. + if (ctrl->irq > 0) {
  62. + /*
  63. + * Some SoCs integrate this controller (e.g., its interrupt bits) in
  64. + * interesting ways
  65. + */
  66. + if (soc) {
  67. + ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
  68. + DRV_NAME, ctrl);
  69. +
  70. + /* Enable interrupt */
  71. + ctrl->soc->ctlrdy_ack(ctrl->soc);
  72. + ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
  73. + } else {
  74. + /* Use standard interrupt infrastructure */
  75. + ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
  76. + DRV_NAME, ctrl);
  77. + }
  78. + if (ret < 0) {
  79. + dev_err(dev, "can't allocate IRQ %d: error %d\n",
  80. + ctrl->irq, ret);
  81. + goto err;
  82. + }
  83. }
  84. for_each_available_child_of_node(dn, child) {