ath79.dtsi 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. / {
  3. #address-cells = <1>;
  4. #size-cells = <1>;
  5. cpuintc: interrupt-controller {
  6. compatible = "qca,ar7100-cpu-intc";
  7. interrupt-controller;
  8. #interrupt-cells = <1>;
  9. };
  10. ahb {
  11. compatible = "simple-bus";
  12. ranges;
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. interrupt-parent = <&cpuintc>;
  16. apb {
  17. compatible = "simple-bus";
  18. ranges;
  19. #address-cells = <1>;
  20. #size-cells = <1>;
  21. interrupt-parent = <&miscintc>;
  22. miscintc: interrupt-controller@18060010 {
  23. compatible = "qca,ar7240-misc-intc";
  24. reg = <0x18060010 0x4>;
  25. interrupt-parent = <&cpuintc>;
  26. interrupts = <6>;
  27. interrupt-controller;
  28. #interrupt-cells = <1>;
  29. };
  30. };
  31. eth0: eth@19000000 {
  32. status = "disabled";
  33. compatible = "qca,ath79-eth", "syscon", "simple-mfd";
  34. reg = <0x19000000 0x200>;
  35. interrupts = <4>;
  36. phy-mode = "mii";
  37. mdio0: mdio-bus {
  38. status = "disabled";
  39. compatible = "qca,ath79-mdio";
  40. #address-cells = <1>;
  41. #size-cells = <0>;
  42. regmap = <&eth0>;
  43. clocks = <&pll ATH79_CLK_MDIO>;
  44. clock-names = "ref";
  45. };
  46. };
  47. eth1: eth@1a000000 {
  48. status = "disabled";
  49. compatible = "qca,ath79-eth", "syscon", "simple-mfd";
  50. reg = <0x1a000000 0x200>;
  51. interrupts = <5>;
  52. phy-mode = "mii";
  53. mdio1: mdio-bus {
  54. status = "disabled";
  55. compatible = "qca,ath79-mdio";
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. regmap = <&eth1>;
  59. clocks = <&pll ATH79_CLK_MDIO>;
  60. clock-names = "ref";
  61. };
  62. };
  63. };
  64. };