qcom-ipq8065-nighthawk.dtsi 7.3 KB

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  1. #include "qcom-ipq8065.dtsi"
  2. #include <dt-bindings/input/input.h>
  3. / {
  4. memory@0 {
  5. reg = <0x42000000 0x1e000000>;
  6. device_type = "memory";
  7. };
  8. reserved-memory {
  9. rsvd@5fe00000 {
  10. reg = <0x5fe00000 0x200000>;
  11. reusable;
  12. };
  13. };
  14. aliases {
  15. label-mac-device = &gmac2;
  16. led-boot = &power_white;
  17. led-failsafe = &power_amber;
  18. led-running = &power_white;
  19. led-upgrade = &power_amber;
  20. mdio-gpio0 = &mdio0;
  21. };
  22. keys {
  23. compatible = "gpio-keys";
  24. pinctrl-0 = <&button_pins>;
  25. pinctrl-names = "default";
  26. wifi {
  27. label = "wifi";
  28. gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
  29. linux,code = <KEY_RFKILL>;
  30. debounce-interval = <60>;
  31. wakeup-source;
  32. };
  33. reset {
  34. label = "reset";
  35. gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  36. linux,code = <KEY_RESTART>;
  37. debounce-interval = <60>;
  38. wakeup-source;
  39. };
  40. wps {
  41. label = "wps";
  42. gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
  43. linux,code = <KEY_WPS_BUTTON>;
  44. debounce-interval = <60>;
  45. wakeup-source;
  46. };
  47. };
  48. leds: leds {
  49. compatible = "gpio-leds";
  50. pinctrl-0 = <&led_pins>;
  51. pinctrl-names = "default";
  52. power_white: power_white {
  53. label = "white:power";
  54. gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
  55. default-state = "keep";
  56. };
  57. power_amber: power_amber {
  58. label = "amber:power";
  59. gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
  60. };
  61. wan_white {
  62. label = "white:wan";
  63. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  64. };
  65. wan_amber {
  66. label = "amber:wan";
  67. gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  68. };
  69. wifi {
  70. label = "white:wifi";
  71. gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
  72. };
  73. wps {
  74. label = "white:wps";
  75. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  76. };
  77. };
  78. };
  79. &qcom_pinmux {
  80. button_pins: button_pins {
  81. mux {
  82. pins = "gpio6", "gpio54", "gpio65";
  83. function = "gpio";
  84. drive-strength = <2>;
  85. bias-pull-up;
  86. };
  87. };
  88. led_pins: led_pins {
  89. mux {
  90. pins = "gpio7", "gpio8", "gpio9",
  91. "gpio22", "gpio23", "gpio24",
  92. "gpio26", "gpio53", "gpio64";
  93. function = "gpio";
  94. drive-strength = <2>;
  95. bias-pull-down;
  96. };
  97. };
  98. mdio0_pins: mdio0_pins {
  99. clk {
  100. pins = "gpio1";
  101. input-disable;
  102. };
  103. };
  104. rgmii2_pins: rgmii2_pins {
  105. tx {
  106. pins = "gpio27", "gpio28", "gpio29",
  107. "gpio30", "gpio31", "gpio32";
  108. input-disable;
  109. };
  110. };
  111. spi_pins: spi_pins {
  112. mux {
  113. pins = "gpio18", "gpio19", "gpio21";
  114. function = "gsbi5";
  115. bias-pull-down;
  116. };
  117. data {
  118. pins = "gpio18", "gpio19";
  119. drive-strength = <10>;
  120. };
  121. cs {
  122. pins = "gpio20";
  123. drive-strength = <10>;
  124. bias-pull-up;
  125. };
  126. clk {
  127. pins = "gpio21";
  128. drive-strength = <12>;
  129. };
  130. };
  131. spi6_pins: spi6_pins {
  132. mux {
  133. pins = "gpio55", "gpio56", "gpio58";
  134. function = "gsbi6";
  135. bias-pull-down;
  136. };
  137. mosi {
  138. pins = "gpio55";
  139. drive-strength = <12>;
  140. };
  141. miso {
  142. pins = "gpio56";
  143. drive-strength = <14>;
  144. };
  145. cs {
  146. pins = "gpio57";
  147. drive-strength = <12>;
  148. bias-pull-up;
  149. };
  150. clk {
  151. pins = "gpio58";
  152. drive-strength = <12>;
  153. };
  154. reset {
  155. pins = "gpio33";
  156. drive-strength = <10>;
  157. bias-pull-down;
  158. output-high;
  159. };
  160. };
  161. usb0_pwr_en_pins: usb0_pwr_en_pins {
  162. mux {
  163. pins = "gpio15";
  164. function = "gpio";
  165. drive-strength = <12>;
  166. bias-pull-down;
  167. output-high;
  168. };
  169. };
  170. usb1_pwr_en_pins: usb1_pwr_en_pins {
  171. mux {
  172. pins = "gpio16", "gpio68";
  173. function = "gpio";
  174. drive-strength = <12>;
  175. bias-pull-down;
  176. output-high;
  177. };
  178. };
  179. };
  180. &nand_controller {
  181. status = "okay";
  182. pinctrl-0 = <&nand_pins>;
  183. pinctrl-names = "default";
  184. nand@0 {
  185. reg = <0>;
  186. compatible = "qcom,nandcs";
  187. nand-ecc-strength = <4>;
  188. nand-bus-width = <8>;
  189. nand-ecc-step-size = <512>;
  190. nand-is-boot-medium;
  191. qcom,boot_pages_size = <0x1180000>;
  192. partitions: partitions {
  193. compatible = "fixed-partitions";
  194. #address-cells = <1>;
  195. #size-cells = <1>;
  196. partition@0 {
  197. label = "qcadata";
  198. reg = <0x0000000 0x0c80000>;
  199. read-only;
  200. };
  201. partition@c80000 {
  202. label = "APPSBL";
  203. reg = <0x0c80000 0x0500000>;
  204. read-only;
  205. };
  206. partition@1180000 {
  207. label = "APPSBLENV";
  208. reg = <0x1180000 0x0080000>;
  209. read-only;
  210. };
  211. art: partition@1200000 {
  212. label = "art";
  213. reg = <0x1200000 0x0140000>;
  214. read-only;
  215. };
  216. partition@1340000 {
  217. label = "artbak";
  218. reg = <0x1340000 0x0140000>;
  219. read-only;
  220. };
  221. partition@1480000 {
  222. label = "kernel";
  223. reg = <0x1480000 0x0400000>;
  224. };
  225. };
  226. };
  227. };
  228. &mdio0 {
  229. status = "okay";
  230. pinctrl-0 = <&mdio0_pins>;
  231. pinctrl-names = "default";
  232. phy0: ethernet-phy@0 {
  233. reg = <0>;
  234. qca,ar8327-initvals = <
  235. 0x00004 0x7600000 /* PAD0_MODE */
  236. 0x00008 0x1000000 /* PAD5_MODE */
  237. 0x0000c 0x80 /* PAD6_MODE */
  238. 0x000e4 0xaa545 /* MAC_POWER_SEL */
  239. 0x000e0 0xc74164de /* SGMII_CTRL */
  240. 0x0007c 0x4e /* PORT0_STATUS */
  241. 0x00094 0x4e /* PORT6_STATUS */
  242. 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */
  243. 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */
  244. 0x00978 0x19008643 /* QM_PORT1_CTRL0 */
  245. 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */
  246. 0x00980 0x19008643 /* QM_PORT2_CTRL0 */
  247. 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */
  248. 0x00988 0x19008643 /* QM_PORT3_CTRL0 */
  249. 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */
  250. 0x00990 0x19008643 /* QM_PORT4_CTRL0 */
  251. 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */
  252. 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */
  253. 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */
  254. 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */
  255. 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */
  256. >;
  257. qca,ar8327-vlans = <
  258. 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */
  259. 0x2 0x21 /* VLAN2 Ports 0/5 */
  260. >;
  261. };
  262. phy4: ethernet-phy@4 {
  263. reg = <4>;
  264. qca,ar8327-initvals = <
  265. 0x000e4 0x6a545 /* MAC_POWER_SEL */
  266. 0x0000c 0x80 /* PAD6_MODE */
  267. >;
  268. };
  269. };
  270. &gmac1 {
  271. status = "okay";
  272. phy-mode = "rgmii";
  273. qcom,id = <1>;
  274. qcom,phy_mdio_addr = <4>;
  275. qcom,poll_required = <0>;
  276. qcom,rgmii_delay = <1>;
  277. qcom,phy_mii_type = <0>;
  278. qcom,emulation = <0>;
  279. qcom,irq = <255>;
  280. mdiobus = <&mdio0>;
  281. pinctrl-0 = <&rgmii2_pins>;
  282. pinctrl-names = "default";
  283. nvmem-cells = <&macaddr_art_6>;
  284. nvmem-cell-names = "mac-address";
  285. fixed-link {
  286. speed = <1000>;
  287. full-duplex;
  288. };
  289. };
  290. &gmac2 {
  291. status = "okay";
  292. phy-mode = "sgmii";
  293. qcom,id = <2>;
  294. qcom,phy_mdio_addr = <0>; /* none */
  295. qcom,poll_required = <0>; /* no polling */
  296. qcom,rgmii_delay = <0>;
  297. qcom,phy_mii_type = <1>;
  298. qcom,emulation = <0>;
  299. qcom,irq = <258>;
  300. mdiobus = <&mdio0>;
  301. nvmem-cells = <&macaddr_art_0>;
  302. nvmem-cell-names = "mac-address";
  303. fixed-link {
  304. speed = <1000>;
  305. full-duplex;
  306. };
  307. };
  308. &adm_dma {
  309. status = "okay";
  310. };
  311. &sata_phy {
  312. status = "okay";
  313. };
  314. &sata {
  315. status = "okay";
  316. };
  317. &usb3_0 {
  318. status = "okay";
  319. pinctrl-0 = <&usb0_pwr_en_pins>;
  320. pinctrl-names = "default";
  321. };
  322. &usb3_1 {
  323. status = "okay";
  324. pinctrl-0 = <&usb1_pwr_en_pins>;
  325. pinctrl-names = "default";
  326. };
  327. &pcie0 {
  328. status = "okay";
  329. bridge@0,0 {
  330. reg = <0x00000000 0 0 0 0>;
  331. #address-cells = <3>;
  332. #size-cells = <2>;
  333. ranges;
  334. wifi0: wifi@1,0 {
  335. compatible = "pci168c,0046";
  336. reg = <0x00010000 0 0 0 0>;
  337. };
  338. };
  339. };
  340. &pcie1 {
  341. status = "okay";
  342. max-link-speed = <1>;
  343. bridge@0,0 {
  344. reg = <0x00000000 0 0 0 0>;
  345. #address-cells = <3>;
  346. #size-cells = <2>;
  347. ranges;
  348. wifi1: wifi@1,0 {
  349. compatible = "pci168c,0046";
  350. reg = <0x00010000 0 0 0 0>;
  351. };
  352. };
  353. };
  354. &art {
  355. compatible = "nvmem-cells";
  356. #address-cells = <1>;
  357. #size-cells = <1>;
  358. macaddr_art_0: macaddr@0 {
  359. reg = <0x0 0x6>;
  360. };
  361. macaddr_art_6: macaddr@6 {
  362. reg = <0x6 0x6>;
  363. };
  364. };