apm82181.dtsi 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Device Tree for Bluestone (APM821xx) board.
  4. *
  5. * Copyright (c) 2010, Applied Micro Circuits Corporation
  6. * Author: Tirumala R Marri <[email protected]>
  7. */
  8. #include <dt-bindings/dma/dw-dmac.h>
  9. #include <dt-bindings/input/input.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. #address-cells = <2>;
  14. #size-cells = <1>;
  15. dcr-parent = <&{/cpus/cpu@0}>;
  16. compatible = "apm,bluestone";
  17. aliases {
  18. ethernet0 = &EMAC0; /* needed for BSP u-boot */
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. CPU0: cpu@0 {
  24. device_type = "cpu";
  25. model = "PowerPC,apm82181";
  26. reg = <0x00000000>;
  27. clock-frequency = <0>; /* Filled in by U-Boot */
  28. timebase-frequency = <0>; /* Filled in by U-Boot */
  29. i-cache-line-size = <32>;
  30. d-cache-line-size = <32>;
  31. i-cache-size = <32768>;
  32. d-cache-size = <32768>;
  33. dcr-controller;
  34. dcr-access-method = "native";
  35. next-level-cache = <&L2C0>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  41. };
  42. UIC0: interrupt-controller0 {
  43. compatible = "apm,uic-apm82181", "ibm,uic";
  44. interrupt-controller;
  45. cell-index = <0>;
  46. dcr-reg = <0x0c0 0x009>;
  47. #address-cells = <0>;
  48. #size-cells = <0>;
  49. #interrupt-cells = <2>;
  50. };
  51. UIC1: interrupt-controller1 {
  52. compatible = "apm,uic-apm82181", "ibm,uic";
  53. interrupt-controller;
  54. cell-index = <1>;
  55. dcr-reg = <0x0d0 0x009>;
  56. #address-cells = <0>;
  57. #size-cells = <0>;
  58. #interrupt-cells = <2>;
  59. interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>,
  60. <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  61. interrupt-parent = <&UIC0>;
  62. };
  63. UIC2: interrupt-controller2 {
  64. compatible = "apm,uic-apm82181", "ibm,uic";
  65. interrupt-controller;
  66. cell-index = <2>;
  67. dcr-reg = <0x0e0 0x009>;
  68. #address-cells = <0>;
  69. #size-cells = <0>;
  70. #interrupt-cells = <2>;
  71. interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>,
  72. <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  73. interrupt-parent = <&UIC0>;
  74. };
  75. UIC3: interrupt-controller3 {
  76. compatible = "apm,uic-apm82181","ibm,uic";
  77. interrupt-controller;
  78. cell-index = <3>;
  79. dcr-reg = <0x0f0 0x009>;
  80. #address-cells = <0>;
  81. #size-cells = <0>;
  82. #interrupt-cells = <2>;
  83. interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>,
  84. <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  85. interrupt-parent = <&UIC0>;
  86. };
  87. OCM1: ocm@400040000 {
  88. compatible = "apm,ocm-apm82181", "ibm,ocm";
  89. status = "okay";
  90. cell-index = <1>;
  91. /* configured in U-Boot */
  92. reg = <4 0x00040000 0x8000>; /* 32K */
  93. };
  94. SDR0: sdr {
  95. compatible = "apm,sdr-apm82181", "ibm,sdr-460ex";
  96. dcr-reg = <0x00e 0x002>;
  97. };
  98. CPR0: cpr {
  99. compatible = "apm,cpr-apm82181", "ibm,cpr-460ex";
  100. dcr-reg = <0x00c 0x002>;
  101. };
  102. L2C0: l2c {
  103. compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
  104. dcr-reg = <0x020 0x008
  105. 0x030 0x008>;
  106. cache-line-size = <32>;
  107. cache-size = <262144>;
  108. interrupt-parent = <&UIC1>;
  109. interrupts = <0x0b IRQ_TYPE_EDGE_RISING>;
  110. };
  111. CPM0: cpm {
  112. compatible = "ibm,cpm-apm821xx", "ibm,cpm";
  113. cell-index = <0>;
  114. dcr-reg = <0x160 0x003>;
  115. pm-cpu = <0x02000000>;
  116. pm-doze = <0x302570F0>;
  117. pm-nap = <0x302570F0>;
  118. pm-deepsleep = <0x302570F0>;
  119. pm-iic-device = <&IIC0>;
  120. pm-emac-device = <&EMAC0>;
  121. unused-units = <0x00000100>;
  122. idle-doze = <0x02000000>;
  123. standby = <0xfeff791d>;
  124. };
  125. plb {
  126. compatible = "apm,plb-apm82181", "ibm,plb-460ex", "ibm,plb4";
  127. #address-cells = <2>;
  128. #size-cells = <1>;
  129. ranges; /* Filled in by U-Boot */
  130. clock-frequency = <0>; /* Filled in by U-Boot */
  131. SDRAM0: sdram {
  132. compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp";
  133. dcr-reg = <0x010 0x002>;
  134. };
  135. RTC: rtc {
  136. compatible = "ibm,rtc";
  137. dcr-reg = <0x240 0x009>;
  138. interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
  139. interrupt-parent = <&UIC2>;
  140. status = "disabled";
  141. };
  142. TRNG: trng@110000 {
  143. compatible = "amcc,ppc460ex-rng", "ppc4xx-rng", "amcc, ppc4xx-trng";
  144. reg = <4 0x00110000 0x100>;
  145. interrupt-parent = <&UIC1>;
  146. interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
  147. status = "disabled";
  148. };
  149. PKA: pka@114000 {
  150. compatible = "ppc4xx-pka", "amcc,ppc4xx-pka", "amcc, ppc4xx-pka";
  151. reg = <4 0x00114000 0x4000>;
  152. interrupt-parent = <&UIC0>;
  153. interrupts = <0x14 IRQ_TYPE_EDGE_RISING>;
  154. status = "disabled";
  155. };
  156. CRYPTO: crypto@180000 {
  157. compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
  158. reg = <4 0x00180000 0x80400>;
  159. interrupt-parent = <&UIC0>;
  160. interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;
  161. status = "disabled"; /* hardware option */
  162. };
  163. MAL0: mcmal {
  164. compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
  165. descriptor-memory = "ocm";
  166. dcr-reg = <0x180 0x062>;
  167. num-tx-chans = <1>;
  168. num-rx-chans = <1>;
  169. #address-cells = <0>;
  170. #size-cells = <0>;
  171. interrupt-parent = <&UIC2>;
  172. interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>,
  173. <0x07 IRQ_TYPE_LEVEL_HIGH>,
  174. <0x03 IRQ_TYPE_LEVEL_HIGH>,
  175. <0x04 IRQ_TYPE_LEVEL_HIGH>,
  176. <0x05 IRQ_TYPE_LEVEL_HIGH>,
  177. <0x08 IRQ_TYPE_EDGE_FALLING>,
  178. <0x09 IRQ_TYPE_EDGE_FALLING>,
  179. <0x0c IRQ_TYPE_EDGE_FALLING>,
  180. <0x0d IRQ_TYPE_EDGE_FALLING>;
  181. interrupt-names = "txeob", "rxeob", "serr",
  182. "txde", "rxde",
  183. "tx0coal", "tx1coal",
  184. "rx0coal", "rx1coal";
  185. };
  186. POB0: opb {
  187. compatible = "ibm,opb-460ex", "ibm,opb";
  188. #address-cells = <1>;
  189. #size-cells = <1>;
  190. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  191. clock-frequency = <0>; /* Filled in by U-Boot */
  192. EBC0: ebc {
  193. compatible = "ibm,ebc-460ex", "ibm,ebc";
  194. dcr-reg = <0x012 0x002>;
  195. #address-cells = <2>;
  196. #size-cells = <1>;
  197. clock-frequency = <0>; /* Filled in by U-Boot */
  198. /* ranges property is supplied by U-Boot */
  199. ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;
  200. interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;
  201. interrupt-parent = <&UIC1>;
  202. nor_flash@0,0 {
  203. compatible = "cfi-flash";
  204. bank-width = <1>;
  205. reg = <0x00000000 0x00000000 0x00100000>;
  206. #address-cells = <1>;
  207. #size-cells = <1>;
  208. status = "disabled";
  209. };
  210. ndfc: ndfc@1,0 {
  211. compatible = "ibm,ndfc";
  212. reg = <00000003 00000000 00002000>;
  213. ccr = <0x00001000>;
  214. bank-settings = <0x80002222>;
  215. status = "disabled";
  216. nand {
  217. /*
  218. * These are the same fixed "MAGIC" values
  219. * settings as in the drivers code.
  220. * They are the same for all devices that
  221. * have NAND.
  222. */
  223. nand-ecc-engine = <&ndfc>;
  224. nand-ecc-algo = "hamming";
  225. nand-ecc-step-size = <256>;
  226. nand-ecc-strength = <1>;
  227. };
  228. };
  229. };
  230. UART0: serial@ef600300 {
  231. /*
  232. * AMCC's BSP u-boot scans for the "ns16550"
  233. * compatible, without it, u-boot wouldn't
  234. * set the required "clock-frequency".
  235. *
  236. * The hardware documentation states:
  237. * "Register compatibility with 16750 register set"
  238. */
  239. compatible = "ns16750", "ns16550";
  240. reg = <0xef600300 0x00000008>;
  241. virtual-reg = <0xef600300>;
  242. clock-frequency = <0>; /* Filled in by U-Boot */
  243. interrupt-parent = <&UIC1>;
  244. interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
  245. status = "disabled";
  246. };
  247. UART1: serial@ef600400 {
  248. /* same "ns16750" as with UART0 */
  249. compatible = "ns16750", "ns16550";
  250. reg = <0xef600400 0x00000008>;
  251. virtual-reg = <0xef600400>;
  252. clock-frequency = <0>; /* Filled in by U-Boot */
  253. interrupt-parent = <&UIC0>;
  254. interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
  255. status = "disabled";
  256. };
  257. IIC0: i2c@ef600700 {
  258. compatible = "ibm,iic-460ex", "ibm,iic";
  259. reg = <0xef600700 0x00000014>;
  260. interrupt-parent = <&UIC0>;
  261. interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. status = "disabled";
  265. };
  266. IIC1: i2c@ef600800 {
  267. compatible = "ibm,iic-460ex", "ibm,iic";
  268. reg = <0xef600800 0x00000014>;
  269. interrupt-parent = <&UIC0>;
  270. interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. status = "disabled";
  274. };
  275. GPIO0: gpio@ef600b00 {
  276. compatible = "ibm,ppc4xx-gpio";
  277. reg = <0xef600b00 0x00000048>;
  278. #gpio-cells = <2>;
  279. gpio-controller;
  280. status = "disabled";
  281. };
  282. EMAC0: ethernet@ef600c00 {
  283. device_type = "network";
  284. compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
  285. interrupt-parent = <&EMAC0>;
  286. interrupts = <0 1>;
  287. #interrupt-cells = <1>;
  288. #address-cells = <0>;
  289. #size-cells = <0>;
  290. interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>,
  291. <1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>;
  292. interrupt-names = "status", "wake";
  293. reg = <0xef600c00 0x000000c4>;
  294. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  295. mal-device = <&MAL0>;
  296. mal-tx-channel = <0>;
  297. mal-rx-channel = <0>;
  298. cell-index = <0>;
  299. max-frame-size = <9000>;
  300. rx-fifo-size = <16384>;
  301. tx-fifo-size = <2048>;
  302. phy-mode = "rgmii";
  303. phy-map = <0x00000000>;
  304. rgmii-device = <&RGMII0>;
  305. rgmii-channel = <0>;
  306. tah-device = <&TAH0>;
  307. tah-channel = <0>;
  308. has-inverted-stacr-oc;
  309. has-new-stacr-staopc;
  310. status = "disabled";
  311. };
  312. TAH0: emac-tah@ef601350 {
  313. compatible = "ibm,tah-460ex", "ibm,tah";
  314. reg = <0xef601350 0x00000030>;
  315. };
  316. RGMII0: emac-rgmii@ef601500 {
  317. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  318. reg = <0xef601500 0x00000008>;
  319. has-mdio;
  320. };
  321. };
  322. USBOTG0: usbotg@bff80000 {
  323. compatible = "amcc,dwc-otg";
  324. reg = <4 0xbff80000 0x10000>;
  325. interrupt-parent = <&USBOTG0>;
  326. interrupts = <0 1 2>;
  327. #interrupt-cells = <1>;
  328. #address-cells = <0>;
  329. #size-cells = <0>;
  330. interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>,
  331. <1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>,
  332. <2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>;
  333. interrupt-names = "usb-otg", "high-power", "dma";
  334. dr_mode = "host";
  335. status = "disabled";
  336. };
  337. AHBDMA0: dma@bffd0800 {
  338. compatible = "snps,dma-spear1340";
  339. reg = <4 0xbffd0800 0x400>;
  340. interrupt-parent = <&UIC0>;
  341. interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;
  342. #dma-cells = <3>;
  343. dma-channels = <2>;
  344. dma-masters = <3>;
  345. block_size = <4095>;
  346. data-width = <4>, <4>, <4>;
  347. multi-block = <1>, <1>;
  348. chan_allocation_order = <1>;
  349. chan_priority = <1>;
  350. snps,dma-protection-control =
  351. <(DW_DMAC_HPROT1_PRIVILEGED_MODE |
  352. DW_DMAC_HPROT2_BUFFERABLE)>;
  353. is_memcpy;
  354. };
  355. SATA0: sata@bffd1000 {
  356. compatible = "amcc,sata-460ex";
  357. reg = <4 0xbffd1000 0x800>;
  358. interrupt-parent = <&UIC0>;
  359. interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
  360. dmas = <&AHBDMA0 0 0 1>;
  361. dma-names = "sata-dma";
  362. status = "disabled";
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. };
  366. SATA1: sata@bffd1800 {
  367. compatible = "amcc,sata-460ex";
  368. reg = <4 0xbffd1800 0x800>;
  369. interrupt-parent = <&UIC0>;
  370. interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;
  371. dmas = <&AHBDMA0 1 0 2>;
  372. dma-names = "sata-dma";
  373. status = "disabled";
  374. #address-cells = <1>;
  375. #size-cells = <0>;
  376. };
  377. PCIE0: pciex@d00000000 {
  378. device_type = "pci"; /* see ppc4xx_pci_find_bridge */
  379. #interrupt-cells = <1>;
  380. #size-cells = <2>;
  381. #address-cells = <3>;
  382. compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
  383. primary;
  384. port = <0x0>; /* port number */
  385. reg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */
  386. <0x0000000c 0x08010000 0x00001000>; /* Registers */
  387. dcr-reg = <0x100 0x020>;
  388. sdr-base = <0x300>;
  389. /*
  390. * Outbound ranges, one memory and one IO,
  391. * later cannot be changed
  392. */
  393. ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>,
  394. <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>,
  395. <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
  396. /* Inbound 2GB range starting at 0 */
  397. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  398. /* This drives busses 0x40 to 0x7f */
  399. bus-range = <0x40 0x7f>;
  400. /*
  401. * Legacy interrupts (note the weird polarity, the bridge seems
  402. * to invert PCIe legacy interrupts).
  403. * We are de-swizzling here because the numbers are actually for
  404. * port of the root complex virtual P2P bridge. But I want
  405. * to avoid putting a node for it in the tree, so the numbers
  406. * below are basically de-swizzled numbers.
  407. * The real slot is on idsel 0, so the swizzling is 1:1
  408. */
  409. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  410. interrupt-map =
  411. <0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */
  412. <0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */
  413. <0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */
  414. <0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */
  415. status = "disabled";
  416. };
  417. };
  418. };